| 2008 |
|---|
| 8 | EE | Chao-Yue Lai,
Chung-Yang Huang,
Kei-Yong Khoo:
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification.
DATE 2008: 813-818 |
| 2007 |
|---|
| 7 | EE | Chi-An Wu,
Ting-Hao Lin,
Chih-Chun Lee,
Chung-Yang Huang:
QuteSAT: a robust circuit-based SAT solver for complex circuit structure.
DATE 2007: 1313-1318 |
| 6 | EE | Chih-Chun Lee,
Jie-Hong Roland Jiang,
Chung-Yang Huang,
Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving.
ICCAD 2007: 227-233 |
| 2001 |
|---|
| 5 | EE | Chung-Yang Huang,
Kwang-Ting Cheng:
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 381-391 (2001) |
| 2000 |
|---|
| 4 | EE | Chung-Yang Huang,
Kwang-Ting Cheng:
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.
DAC 2000: 118-123 |
| 3 | | Chung-Yang Huang,
Bwolen Yang,
Huan-Chih Tsai,
Kwang-Ting Cheng:
Static property checking using ATPG vs. BDD techniques.
ITC 2000: 309-316 |
| 2 | EE | Shi-Yu Huang,
Kwang-Ting Cheng,
Kuang-Chien Chen,
Chung-Yang Huang,
Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs.
IEEE Trans. Computers 49(5): 443-464 (2000) |
| 1998 |
|---|
| 1 | EE | Chung-Yang Huang,
Yucheng Wang,
Kwang-Ting Cheng:
LIBRA - a library-independent framework for post-layout performance optimization.
ISPD 1998: 135-140 |
