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Kent L. Einspahr

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2001
7EEMark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Design Verification and Functional Testing of FiniteState Machines. VLSI Design 2001: 189-195
2000
6 Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Exploiting don't cares to enhance functional tests. ITC 2000: 538-546
1999
5EEKent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: A synthesis for testability scheme for finite state machines using clock control. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1780-1792 (1999)
1998
4EEKent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472-
1997
3EEShashank K. Mehta, Kent L. Einspahr, Sharad C. Seth: Synthesis for Testability by Two-Clock Control. VLSI Design 1997: 279-283
1996
2EEKent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293
1995
1EEKent L. Einspahr, Sharad C. Seth: A switch-level test generation system for synchronous and asynchronous circuits. J. Electronic Testing 6(1): 59-73 (1995)

Coauthor Index

1Vishwani D. Agrawal [2]
2Shashank K. Mehta [3] [4] [5] [6] [7]
3Sharad C. Seth [1] [2] [3] [4] [5] [6] [7]
4Mark W. Weiss [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)