| 2001 |
|---|
| 7 | EE | Mark W. Weiss,
Sharad C. Seth,
Shashank K. Mehta,
Kent L. Einspahr:
Design Verification and Functional Testing of FiniteState Machines.
VLSI Design 2001: 189-195 |
| 2000 |
|---|
| 6 | | Mark W. Weiss,
Sharad C. Seth,
Shashank K. Mehta,
Kent L. Einspahr:
Exploiting don't cares to enhance functional tests.
ITC 2000: 538-546 |
| 1999 |
|---|
| 5 | EE | Kent L. Einspahr,
Shashank K. Mehta,
Sharad C. Seth:
A synthesis for testability scheme for finite state machines using clock control.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1780-1792 (1999) |
| 1998 |
|---|
| 4 | EE | Kent L. Einspahr,
Shashank K. Mehta,
Sharad C. Seth:
Synthesis of Sequential Circuits with Clock Control to Improve Testability.
Asian Test Symposium 1998: 472- |
| 1997 |
|---|
| 3 | EE | Shashank K. Mehta,
Kent L. Einspahr,
Sharad C. Seth:
Synthesis for Testability by Two-Clock Control.
VLSI Design 1997: 279-283 |
| 1996 |
|---|
| 2 | EE | Kent L. Einspahr,
Sharad C. Seth,
Vishwani D. Agrawal:
Improving Circuit Testability by Clock Control.
Great Lakes Symposium on VLSI 1996: 288-293 |
| 1995 |
|---|
| 1 | EE | Kent L. Einspahr,
Sharad C. Seth:
A switch-level test generation system for synchronous and asynchronous circuits.
J. Electronic Testing 6(1): 59-73 (1995) |
