| 2007 |
|---|
| 28 | EE | Claude Thibeault:
On a New Outlier Rejection Technique.
VTS 2007: 97-103 |
| 2004 |
|---|
| 27 | EE | Claude Thibeault:
On New Current Signatures and Adaptive Test Technique Combination.
VTS 2004: 59-64 |
| 2003 |
|---|
| 26 | EE | Y. Hariri,
Claude Thibeault:
3DSDM: A 3 Data-Source Diagnostic Method.
DFT 2003: 117-123 |
| 25 | EE | Claude Thibeault:
Replacing IDDQ Testing: With Variance Reduction.
J. Electronic Testing 19(3): 325-340 (2003) |
| 24 | EE | Claude Thibeault:
On Faster IDDQ Measurements.
J. Electronic Testing 19(6): 625-635 (2003) |
| 2002 |
|---|
| 23 | EE | Bing Qiu,
Yvon Savaria,
Meng Lu,
Chunyan Wang,
Claude Thibeault:
Yield Modeling of a WSI Telecom Router Architecture.
DFT 2002: 314-324 |
| 22 | EE | Claude Thibeault:
Speeding-Up IDDQ Measurements.
VTS 2002: 295-301 |
| 2001 |
|---|
| 21 | EE | Ginette Monté,
Bernard Antaki,
Serge Patenaude,
Yvon Savaria,
Claude Thibeault,
Pieter M. Trouborst:
Tools for the Characterization of Bipolar CML Testability.
VTS 2001: 388-395 |
| 2000 |
|---|
| 20 | | Claude Thibeault:
Improving Delta-I_DDQ-based test methods.
ITC 2000: 207-216 |
| 19 | EE | Claude Thibeault:
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.
VTS 2000: 431-438 |
| 18 | EE | Claude Thibeault:
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults.
IEEE Trans. Computers 49(6): 575-587 (2000) |
| 17 | EE | Claude Thibeault:
Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results.
J. Electronic Testing 16(4): 339-353 (2000) |
| 1999 |
|---|
| 16 | | Claude Thibeault:
An histogram based procedure for current testing of active defects.
ITC 1999: 714-723 |
| 15 | EE | Claude Thibeault:
On the Comparison of IDDQ and IDDQ Testing.
VTS 1999: 143-151 |
| 14 | | Claude Thibeault,
Guy Bégin:
A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations.
IEEE Trans. Computers 48(6): 615-627 (1999) |
| 1998 |
|---|
| 13 | EE | Claude Thibeault:
Increasing Current Testing Resolution.
DFT 1998: 126-134 |
| 12 | EE | Claude Thibeault,
Luc Boisvert:
On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis.
DFT 1998: 202-210 |
| 11 | EE | Claude Thibeault,
Luc Boisvert:
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results.
ITC 1998: 1019-1026 |
| 1997 |
|---|
| 10 | EE | Michel Kafrouni,
Claude Thibeault,
Yvon Savaria:
A Cost Model for VLSI / MCM Systems.
DFT 1997: 148-156 |
| 9 | EE | Yves Gagnon,
Yvon Savaria,
Michel Meunier,
Claude Thibeault:
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.
DFT 1997: 157-165 |
| 8 | EE | Claude Thibeault:
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures.
VTS 1997: 80-87 |
| 1996 |
|---|
| 7 | | Yervant Zorian,
Tom Anderson,
Yvon Savaria,
Claude Thibeault,
André Ivanov:
Panel Summaries.
IEEE Design & Test of Computers 13(3): 6, 110-112 (1996) |
| 1995 |
|---|
| 6 | EE | Claude Thibeault:
Detection and location of faults and defects using digital signal processing.
VTS 1995: 262-269 |
| 5 | | Claude Thibeault,
Yvon Savaria,
Jean-Louis Houle:
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers 44(5): 724-728 (1995) |
| 1994 |
|---|
| 4 | | Claude Thibeault:
Using Fourier Analysis to Enhance IC Testability.
DFT 1994: 280-298 |
| 3 | | Claude Thibeault,
Yvon Savaria,
Jean-Louis Houle:
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers 43(6): 687-698 (1994) |
| 1993 |
|---|
| 2 | | J. Crépeau,
Claude Thibeault,
Yvon Savaria:
Some Results on Yield and Local Design Rule Relaxation.
DFT 1993: 144-151 |
| 1992 |
|---|
| 1 | EE | Claude Thibeault,
Yvon Savaria,
Jean-Louis Houle:
Test quality of hierarchical defect-tolerant integrated circuits.
J. Electronic Testing 3(1): 93-102 (1992) |
