| 2002 |
|---|
| 8 | EE | Mondira Deb Pant,
Pankaj Pant,
D. Scott Wills:
On-chip decoupling capacitor optimization using architectural level prediction.
IEEE Trans. VLSI Syst. 10(3): 319-326 (2002) |
| 2001 |
|---|
| 7 | EE | Pankaj Pant,
Yuan-Chieh Hsu,
Sandeep K. Gupta,
Abhijit Chatterjee:
Path delay fault diagnosis in combinational circuits with implicitfault enumeration.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1226-1235 (2001) |
| 2000 |
|---|
| 6 | | Pankaj Pant,
Abhijit Chatterjee:
Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application.
ITC 2000: 245-252 |
| 5 | EE | Mondira Deb Pant,
Pankaj Pant,
D. Scott Wills,
Vivek Tiwari:
Inductive Noise Reduction at the Architectural Level.
VLSI Design 2000: 162-167 |
| 1999 |
|---|
| 4 | EE | Pankaj Pant,
Abhijit Chatterjee:
Efficient diagnosis of path delay faults in digital logic circuits.
ICCAD 1999: 471-476 |
| 3 | EE | Mondira Deb Pant,
Pankaj Pant,
D. Scott Wills,
Vivek Tiwari:
An architectural solution for the inductive noise problem due to clock-gating.
ISLPED 1999: 255-257 |
| 1997 |
|---|
| 2 | EE | Pankaj Pant,
Vivek De,
Abhijit Chatterjee:
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.
DAC 1997: 403-408 |
| 1996 |
|---|
| 1 | EE | Abhijit Chatterjee,
Rathish Jayabharathi,
Pankaj Pant,
Jacob A. Abraham:
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
VTS 1996: 354-361 |
