| 2000 |
|---|
| 7 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Vishwani D. Agrawal:
A testability metric for path delay faults and its application.
ASP-DAC 2000: 593-598 |
| 6 | | Chung-Yang Huang,
Bwolen Yang,
Huan-Chih Tsai,
Kwang-Ting Cheng:
Static property checking using ATPG vs. BDD techniques.
ITC 2000: 309-316 |
| 5 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Sudipta Bhawmik:
On improving test quality of scan-based BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 928-938 (2000) |
| 1999 |
|---|
| 4 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Sudipta Bhawmik:
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme.
DAC 1999: 748-753 |
| 1998 |
|---|
| 3 | EE | Huan-Chih Tsai,
Sudipta Bhawmik,
Kwang-Ting Cheng:
An almost full-scan BIST solution-higher fault coverage and shorter test application time.
ITC 1998: 1065- |
| 2 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Chih-Jen Lin,
Sudipta Bhawmik:
Efficient test-point selection for scan-based BIST.
IEEE Trans. VLSI Syst. 6(4): 667-676 (1998) |
| 1997 |
|---|
| 1 | EE | Huan-Chih Tsai,
Kwang-Ting Cheng,
Chih-Jen Lin,
Sudipta Bhawmik:
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.
DAC 1997: 478-483 |
