| 2004 |
|---|
| 9 | EE | Abhijit Jas,
Bahram Pouya,
Nur A. Touba:
Test data compression technique for embedded cores using virtual scan chains.
IEEE Trans. VLSI Syst. 12(7): 775-781 (2004) |
| 2001 |
|---|
| 8 | EE | Ranganathan Sankaralingam,
Nur A. Touba,
Bahram Pouya:
Reducing Power Dissipation during Test Using Scan Chain Disable.
VTS 2001: 319-325 |
| 2000 |
|---|
| 7 | | Bahram Pouya,
Alfred L. Crouch:
Optimization trade-offs for vector volume and test power.
ITC 2000: 873-881 |
| 6 | EE | Abhijit Jas,
Bahram Pouya,
Nur A. Touba:
Virtual Scan Chains: A Means for Reducing Scan Length in Cores.
VTS 2000: 73-78 |
| 1998 |
|---|
| 5 | EE | Zhe Zhao,
Bahram Pouya,
Nur A. Touba:
BETSY: synthesizing circuits for a specified BIST environment.
ITC 1998: 144-153 |
| 4 | EE | Bahram Pouya,
Nur A. Touba:
Synthesis of Zero-Aliasing Elementary-Tree Space Compactors.
VTS 1998: 70-77 |
| 1997 |
|---|
| 3 | | Bahram Pouya,
Nur A. Touba:
Modifying User-Defined Logic for Test Access to Embedded Cores.
ITC 1997: 60-68 |
| 2 | EE | Nur A. Touba,
Bahram Pouya:
Testing Embedded Cores Using Partial Isolation Rings.
VTS 1997: 10-16 |
| 1 | EE | Nur A. Touba,
Bahram Pouya:
Using Partial Isolation Rings to Test Core-Based Designs.
IEEE Design & Test of Computers 14(4): 52-59 (1997) |
