Mircea Vladutiu

2009
29	EE	Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Quantum Circuit Synthesis with Adaptive Parameters Control. EuroGP 2009: 339-350
2008
28	EE	Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo: Floating point multiplication rounding schemes for interval arithmetic. ASAP 2008: 19-24
27	EE	Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu: A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. DDECS 2008: 146-149
26	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Fault-Tolerant Memory Design and Partitioning Issues in Embryonics. ICES 2008: 372-381
25	EE	Versavia Ancusa, Razvan Bogdan, Mircea Vladutiu: Discussing Redundancy Issues in Intelligent Agent-Based Non-traditional Grids. KES (2) 2008: 297-305
2007
24	EE	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits. Annual Simulation Symposium 2007: 213-220
23		Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo: Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. DDECS 2007: 223-226
22	EE	Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo: Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. DSD 2007: 132-137
21	EE	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. DSD 2007: 634-640
20	EE	Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Automatic Synthesis for Quantum Circuits Using Genetic Algorithms. ICANNGA (1) 2007: 174-183
19	EE	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai: Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. SACI 2007: 245-250
18	EE	Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: A Genetic Algorithm Framework Applied to Quantum Circuit Synthesis. NICSO 2007: 419-429
17	EE	Lucian Prodan, Mihai Udrescu, Oana Boncalo, Mircea Vladutiu: Design for dependability in emerging technologies. JETC 3(2): (2007)
2006
16	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: A dependability perspective on emerging technologies. Conf. Computing Frontiers 2006: 187-198
15	EE	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Implementing quantum genetic algorithms: a solution based on Grover's algorithm. Conf. Computing Frontiers 2006: 71-82
2005
14	EE	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation. Annual Simulation Symposium 2005: 217-224
13	EE	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Improving quantum circuit dependability with reconfigurable quantum gate arrays. Conf. Computing Frontiers 2005: 133-144
12	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Reliability assessment in embryonics inspired by fault-tolerant quantum computation. Conf. Computing Frontiers 2005: 323-333
11	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Survivability of Embryonic Memories: Analysis and Design Principles. Evolvable Hardware 2005: 280-289
10	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Multiple-level concatenated coding in embryonics: a dependability analysis. GECCO 2005: 941-948
2004
9	EE	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu: Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation. Conf. Computing Frontiers 2004: 96-110
8	EE	Lucian Prodan, Mihai Udrescu, Mircea Vladutiu: Self-Repairing Embryonic Memory Arrays. Evolvable Hardware 2004: 130-137
7	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. J. Electronic Testing 20(1): 61-78 (2004)
2001
6	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. IEEE International Workshop on Rapid System Prototyping 2001: 162-167
5	EE	V. Muresan, Xiaojun Wang, Mircea Vladutiu: A combined tree growing technique for block-test scheduling under power constraints. ISCAS (5) 2001: 255-258
2000
4	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Asian Test Symposium 2000: 465-470
3	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: Power-Constrained Block-Test List Scheduling. IEEE International Workshop on Rapid System Prototyping 2000: 182-187
2		Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: A comparison of classical scheduling approaches in power-constrained block-test scheduling. ITC 2000: 882-891
1	EE	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu: The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. VTS 2000: 417-422

Coauthor Index

1	Alexandru Amaricai	[19] [21] [22] [23] [24] [27] [28]
2	Versavia Ancusa	[25]
3	Razvan Bogdan	[25]
4	Oana Boncalo	[17] [19] [21] [22] [23] [24] [28]
5	V. Muresan	[5]
6	Valentin Muresan	[1] [2] [3] [4] [6] [7]
7	Valentina Muresan	[1] [2] [3] [4] [6] [7]
8	Virgil E. Petcu	[27]
9	Lucian Prodan	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [26] [28] [29]
10	Cristian Ruican	[18] [20] [29]
11	Mihai Udrescu	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [26] [28] [29]
12	Xiaojun Wang	[1] [2] [3] [4] [5] [6] [7]

Colors in the list of coauthors