| 2007 |
|---|
| 13 | EE | Zhenning Shangguan,
Zhipeng Gao,
Kai Zhu:
Ontology-Based Process Modeling Using eTOM and ITIL.
CONFENIS (2) 2007: 1001-1010 |
| 12 | EE | Kai Zhu:
Post-route LUT output polarity selection for timing optimization.
FPGA 2007: 89-96 |
| 2003 |
|---|
| 11 | EE | Yao-Wen Chang,
Kai Zhu,
Guang-Ming Wu,
D. F. Wong,
C. K. Wong:
Analysis of FPGA/FPIC switch modules.
ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003) |
| 2001 |
|---|
| 10 | EE | Kai Zhu,
Yan Zhuang,
Yannis Viniotis:
Achieving End-to-end Delay Bounds by EDF Scheduling without Traffic Shaping.
INFOCOM 2001: 1493-1501 |
| 2000 |
|---|
| 9 | EE | Yao-Wen Chang,
Kai Zhu,
D. F. Wong:
Timing-driven routing for symmetrical array-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000) |
| 1998 |
|---|
| 8 | EE | Huiqun Liu,
Kai Zhu,
D. F. Wong:
Circuit Partitioning with Complex Resource Constraints in FPGAs.
FPGA 1998: 77-84 |
| 7 | EE | Kai Zhu,
Martin D. F. Wong:
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 316-323 (1998) |
| 1997 |
|---|
| 6 | EE | Kai Zhu,
Martin D. F. Wong:
Clock skew minimization during FPGA placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 376-385 (1997) |
| 1994 |
|---|
| 5 | EE | Kai Zhu,
D. F. Wong:
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs.
DAC 1994: 165-170 |
| 4 | EE | Kai Zhu,
D. F. Wong:
Clock Skew Minimization During FPGA Placement.
DAC 1994: 232-237 |
| 3 | EE | Yao-Wen Chang,
Shashidhar Thakur,
Kai Zhu,
D. F. Wong:
A new global routing algorithm for FPGAs.
ICCAD 1994: 356-361 |
| 1993 |
|---|
| 2 | EE | Kai Zhu,
D. F. Wong,
Yao-Wen Chang:
Switch module design with application to two-dimensional segmentation design.
ICCAD 1993: 480-485 |
| 1992 |
|---|
| 1 | EE | Kai Zhu,
D. F. Wong:
On channel segmentation design for row-based FPGAs.
ICCAD 1992: 26-29 |
