Peichen Pan

2008
23	EE	Peichen Pan: Sequential Circuit Technology Mapping. Encyclopedia of Algorithms 2008
2006
22	EE	Deming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3): (2006)
2002
21	EE	Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya: Monotone bipartitioning problem in a planar point set with applications to VLSI. ACM Trans. Design Autom. Electr. Syst. 7(2): 231-248 (2002)
1999
20	EE	Peichen Pan: Performance-Driven Integration of Retiming and Resynthesis. DAC 1999: 243-246
19	EE	Peichen Pan, Guohua Chen: Optimal Retiming for Initial State Computation. VLSI Design 1999: 366-371
18	EE	Prashant Saxena, Peichen Pan, C. L. Liu: The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407
17		Peichen Pan, C. L. Liu: Partial Scan with Preselected Scan Signals. IEEE Trans. Computers 48(9): 1000-1005 (1999)
1998
16	EE	Peichen Pan, Chih-Chang Lin: A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. FPGA 1998: 35-42
15	EE	Unni Narayanan, Peichen Pan, C. L. Liu: Low power logic synthesis under a general delay model. ISLPED 1998: 209-214
14	EE	Peichen Pan, C. L. Liu: Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 3(3): 437-462 (1998)
13	EE	Peichen Pan, Arvind K. Karandikar, C. L. Liu: Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 489-498 (1998)
1997
12		Peichen Pan: Continuous Retiming: Algorithms and Applications. ICCD 1997: 116-121
11		Arvind K. Karandikar, Peichen Pan, C. L. Liu: Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD 1997: 122-127
10		Peichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica 18(4): 560-574 (1997)
1996
9	EE	Peichen Pan, C. L. Liu: Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC 1996: 720-725
8	EE	Xiangfeng Chen, Peichen Pan, C. L. Liu: Desensitization for Power Reduction in Sequential Circuits. DAC 1996: 795-800
7	EE	Peichen Pan, C. L. Liu: Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA 1996: 58-64
6		Peichen Pan, Weiping Shi, C. L. Liu: Area Minimization for Hierarchical Floorplans. Algorithmica 15(6): 550-571 (1996)
1995
5	EE	Peichen Pan, C. L. Liu: Partial Scan with Pre-selected Scan Signals. DAC 1995: 189-194
4	EE	Peichen Pan, C. L. Liu: Area minimization for floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 123-132 (1995)
1994
3	EE	Peichen Pan, Weiping Shi, C. L. Liu: Area minimization for hierarchical floorplans. ICCAD 1994: 436-440
1993
2	EE	Peichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC 1993: 401-406
1992
1	EE	Peichen Pan, C. L. Liu: Area minimization for general floorplans. ICCAD 1992: 606-609

Coauthor Index

1	Bhargab B. Bhattacharya	[21]
2	Deming Chen	[22]
3	Guohua Chen	[19]
4	Xiangfeng Chen	[8]
5	Jason Cong	[22]
6	Parthasarathi Dasgupta (P. S. Dasgupta)	[21]
7	Sai-keung Dong	[2] [10]
8	Arvind K. Karandikar	[11] [13]
9	Chih-Chang Lin	[16]
10	C. L. Liu (Chung Laung (Dave) Liu)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [17] [18]
11	Subhas C. Nandy	[21]
12	Unni Narayanan	[15]
13	Prashant Saxena	[18]
14	Weiping Shi	[3] [6]

Colors in the list of coauthors