Alexander Saldanha

2000
28	EE	Eugene Goldberg, Alexander Saldanha: Timing Analysis with Implicitly Specified False Paths. VLSI Design 2000: 518-522
1999
27	EE	Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli: A methodology for correct-by-construction latency insensitive design. ICCAD 1999: 309-315
26	EE	Alexander Saldanha: Functional timing optimization. ICCAD 1999: 539-543
1998
25	EE	Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha: An Exact Input Encoding Algorithm for BDDs Representing FSMs. Great Lakes Symposium on VLSI 1998: 294-300
24	EE	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin: Partial-scan delay fault testing of asynchronous circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1184-1199 (1998)
1997
23	EE	Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton: Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181
22	EE	Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli: Trace driven logic synthesis&mdashapplication to power minimization. ICCAD 1997: 581-588
21	EE	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin: Partial scan delay fault testing of asynchronous circuits. ICCAD 1997: 728-735
20	EE	Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Symbolic two-level minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 692-708 (1997)
1996
19	EE	Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha: Verification of Electronic Systems. DAC 1996: 106-111
18	EE	Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Compact and complete test set generation for multiple stuck-faults. ICCAD 1996: 212-219
1995
17		Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha: Supervisory Control of Finite State Machines. CAV 1995: 279-292
16	EE	Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli: Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. DAC 1995: 254-260
15	EE	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia: Fast discrete function evaluation using decision diagrams. ICCAD 1995: 402-407
14	EE	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Functional clock schedule optimization. VLSI Design 1995: 93-98
13	EE	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 32-44 (1995)
1994
12	EE	Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Optimization Using Exact Sensitization. DAC 1994: 425-429
11	EE	Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Satisfaction of input and output encoding constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 589-602 (1994)
10	EE	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Circuit structure relations to redundancy and delay. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 875-883 (1994)
1993
9	EE	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Delay Fault Coverage and Performance Tradeoffs. DAC 1993: 446-452
1992
8	EE	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC 1992: 173-176
7	EE	Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC 1992: 245-248
1991
6	EE	Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A Framework for Satisfying Input and Output Encoding Constraints. DAC 1991: 170-175
5		Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD 1991: 180-183
4	EE	Kurt Keutzer, Sharad Malik, Alexander Saldanha: Is redundancy necessary to reduce delay? IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 427-435 (1991)
1990
3	EE	Kurt Keutzer, Sharad Malik, Alexander Saldanha: Is Redundancy Necessary to Reduce Delay. DAC 1990: 228-234
2		Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng: Timing Optimization with Testability Considerations. ICCAD 1990: 460-463
1989
1	EE	Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Multi-level Logic Simplification Using Don't Cares and Filters. DAC 1989: 277-282

Coauthor Index

1	Alok Agrawal	[18]
2	Adnan Aziz	[17]
3	Felice Balarin	[17]
4	Robert K. Brayton	[1] [2] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [17] [20] [23]
5	Luca P. Carloni	[22] [27]
6	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[2]
7	M. D. DiBenedetto	[17]
8	Eugene Goldberg (Evguenii I. Goldberg)	[28]
9	Wilsin Gosti	[23] [25]
10	Heather Harkness	[12]
11	Kurt Keutzer	[3] [4]
12	Michael Kishinevsky	[21] [24]
13	Alex Kondratyev	[21] [24]
14	Yuji Kukimoto	[23]
15	William K. C. Lam	[9] [13]
16	Luciano Lavagno	[16] [18] [21] [24]
17	Sharad Malik	[3] [4]
18	Patrick C. McGeer	[5] [12] [15] [16] [19] [22]
19	Kenneth L. McMillan	[15] [27]
20	Alberto L. Sangiovanni-Vincentelli	[1] [2] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [20] [22] [25] [27]
21	Patrick Scaglia	[15]
22	Narendra V. Shenoy	[14]
23	Paul R. Stephan	[5]
24	Alexander Taubin	[21] [24]
25	Tiziano Villa	[6] [11] [20] [25]
26	Albert R. Wang	[1]