| 1999 |
|---|
| 11 | EE | Chih-Chang Lin,
Kuang-Chien Chen,
Malgorzata Marek-Sadowska:
Logic synthesis for engineering change.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 282-292 (1999) |
| 1998 |
|---|
| 10 | EE | Peichen Pan,
Chih-Chang Lin:
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.
FPGA 1998: 35-42 |
| 9 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng,
Mike Tien-Chien Lee:
Test-point insertion: scan paths through functional logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 838-851 (1998) |
| 8 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Mike Tien-Chien Lee,
Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 852-861 (1998) |
| 1997 |
|---|
| 7 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska:
On designing universal logic blocks and their application to FPGA design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 519-527 (1997) |
| 1996 |
|---|
| 6 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng,
Mike Tien-Chien Lee:
Test Point Insertion: Scan Paths through Combinational Logic.
DAC 1996: 268-273 |
| 1995 |
|---|
| 5 | EE | Chih-Chang Lin,
David Ihsin Cheng,
Malgorzata Marek-Sadowska,
Kuang-Chien Chen:
Logic rectification and synthesis for engineering change.
ASP-DAC 1995 |
| 4 | EE | Chih-Chang Lin,
Kuang-Chien Chen,
Shih-Chieh Chang,
Malgorzata Marek-Sadowska,
Kwang-Ting Cheng:
Logic Synthesis for Engineering Change.
DAC 1995: 647-652 |
| 3 | EE | Chih-Chang Lin,
Mike Tien-Chien Lee,
Malgorzata Marek-Sadowska,
Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology.
ICCAD 1995: 528-533 |
| 2 | EE | David Ihsin Cheng,
Chih-Chang Lin,
Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation.
ICCAD 1995: 650-655 |
| 1994 |
|---|
| 1 | EE | Chih-Chang Lin,
Malgorzata Marek-Sadowska,
Duane Gatlin:
Universal logic gate for FPGA design.
ICCAD 1994: 164-168 |
