| 2008 |
|---|
| 11 | EE | Chang Wu,
Yubai Li,
Song Chai,
Zhongming Yang:
Lottery Router: A Customized Arbitral Priority NOC Router.
CSSE (3) 2008: 411-414 |
| 10 | EE | Song Chai,
Chang Wu,
Yubai Li,
Zhongming Yang:
A NoC Simulation and Verification Platform Based on SystemC.
CSSE (3) 2008: 423-426 |
| 2002 |
|---|
| 9 | EE | Jason Cong,
Chang Wu:
Global clustering-based performance-driven circuit partitioning.
ISPD 2002: 149-154 |
| 2000 |
|---|
| 8 | EE | Jason Cong,
Sung Kyu Lim,
Chang Wu:
Performance driven multi-level and multiway partitioning with retiming.
DAC 2000: 274-279 |
| 1999 |
|---|
| 7 | EE | Jason Cong,
Honching Li,
Chang Wu:
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization.
DAC 1999: 460-465 |
| 6 | EE | Jason Cong,
Chang Wu,
Yuzheng Ding:
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.
FPGA 1999: 29-35 |
| 5 | EE | Jason Cong,
Chang Wu:
Optimal FPGA mapping and retiming with efficient initial state computation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1595-1607 (1999) |
| 1998 |
|---|
| 4 | EE | Jason Cong,
Chang Wu:
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation.
DAC 1998: 330-335 |
| 3 | EE | Jason Cong,
Chang Wu:
An efficient algorithm for performance-optimal FPGA technology mapping with retiming.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 738-748 (1998) |
| 1997 |
|---|
| 2 | EE | Jason Cong,
Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.
DAC 1997: 644-649 |
| 1996 |
|---|
| 1 | EE | Jason Cong,
Chang Wu:
An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.
ICCD 1996: 572-578 |
