| |
| 1998 | ||
|---|---|---|
| 1 | EE | Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto: Clock skew reduction in ASIC logic design: a methodology for clock tree management. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 344-356 (1998) |
| 1 | Alessandro Balboni | [1] |
| 2 | Claudio Costi | [1] |
| 3 | Massimo Pellencin | [1] |
| 4 | Donatella Sciuto | [1] |