| |
| 1999 | ||
|---|---|---|
| 6 | EE | Huiqun Liu, D. F. Wong: Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA 1999: 187-194 |
| 5 | EE | Huiqun Liu, D. F. Wong: A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD 1999: 400-405 |
| 1998 | ||
| 4 | EE | Huiqun Liu, Kai Zhu, D. F. Wong: Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA 1998: 77-84 |
| 3 | EE | Huiqun Liu, D. F. Wong: Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD 1998: 497-504 |
| 2 | EE | Huiqun Liu, Martin D. F. Wong: Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 50-59 (1998) |
| 1997 | ||
| 1 | EE | Huiqun Liu, D. F. Wong: Network flow based multi-way partitioning with area and pin constraints. ISPD 1997: 12-17 |
| 1 | Martin D. F. Wong (D. F. Wong) | [1] [2] [3] [4] [5] [6] |
| 2 | Kai Zhu | [4] |