2009 | ||
---|---|---|
49 | EE | Ying-Cherng Lan, Michael C. Chen, Wei-De. Chen, Sao-Jie Chen, Yu Hen Hu: Performance-energy tradeoffs in reliable NoCs. ISQED 2009: 141-146 |
48 | EE | Chin-Fu Ku, Yu-Fang Zheng, Sao-Jie Chen, Jan-Ming Ho: USVoD: A Large Scale Video-on-Demand System Based on Uniform Sampling Cache Mechanism. J. Inf. Sci. Eng. 25(1): 219-233 (2009) |
2008 | ||
47 | EE | Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen: Flow Maximization for NoC Routing Algorithms. ISVLSI 2008: 335-340 |
46 | EE | Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen: Fluidity concept for NoC: A congestion avoidance and relief routing scheme. SoCC 2008: 65-70 |
45 | EE | Po-Hsun Cheng, Sao-Jie Chen, Jin-Shin Lai, Feipei Lai: A Collaborative Knowledge Management Process for Implementing Healthcare Enterprise Information Systems. IEICE Transactions 91-D(6): 1664-1672 (2008) |
2007 | ||
44 | EE | Yaw-Jen Lin, Mei-Ju Su, Sao-Jie Chen, Suh-Chin Wang, Chiu-I Lin, Heng-Shuen Chen: A Study of Ubiquitous Monitor with RFID in an Elderly Nursing Home. MUE 2007: 336-340 |
43 | EE | Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen: Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts. SAFECOMP 2007: 451-464 |
2006 | ||
42 | EE | Chia-Hsiung Chen, Sao-Jie Chen, Pei-Yung Hsiao: Edge Detection on the Bayer Pattern. APCCAS 2006: 1132-1135 |
41 | EE | Ya-Nan Wen, Guan-Lin Wu, Sao-Jie Chen, Yu Hen Hu: Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC. APCCAS 2006: 1240-1243 |
40 | EE | Guang-Huei Lin, Sao-Jie Chen, R. B. Lee, Yu Hen Hu: Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor. APCCAS 2006: 566-569 |
39 | EE | Pei-Yung Hsiao, Chia-Hsiung Chen, Shin-Shian Chou, Le-Tien Li, Sao-Jie Chen: A parameterizable digital-approximated 2D Gaussian smoothing filter for edge detection in noisy image. ISCAS 2006 |
38 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with jumper insertion for antenna avoidance. Integration 39(4): 420-432 (2006) |
2005 | ||
37 | EE | Chin-Fu Ku, Sao-Jie Chen, Jan-Ming Ho, Ray-I Chang: Improving End-to-End Performance by Active Queue Management. AINA 2005: 337-340 |
36 | EE | Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen: Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602 |
35 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 869-878 (2005) |
34 | EE | Yong-Hsiang Hsieh, Wei-Yi Hu, Wen-Kai Li, Shin-Ming Lin, Chao-Liang Chen, David J. Chen, Sao-Jie Chen: A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver. IEICE Transactions 88-C(8): 1716-1722 (2005) |
2004 | ||
33 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with antenna avoidance. ISPD 2004: 34-40 |
32 | EE | Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen: Fast postplacement optimization using functional symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 102-118 (2004) |
2003 | ||
31 | EE | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387 |
30 | EE | Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: A crosstalk aware two-pin net router. ISCAS (5) 2003: 485-488 |
29 | EE | Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) 2003: 509-512 |
28 | EE | Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen: Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338 |
27 | EE | Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen: Software Platform for Embedded Software Development. RTCSA 2003: 545-557 |
26 | EE | Jong-Sheng Cherng, Sao-Jie Chen: An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. VLSI Design 2003: 70- |
2002 | ||
25 | EE | Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen: Printed circuit board routing and package layout codesign. APCCAS (1) 2002: 155-158 |
24 | EE | Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen: TCN: Scalable Hierarchical Hypercubes. ICPADS 2002: 11-16 |
23 | EE | Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen: VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. Symposium on Object-Oriented Real-Time Distributed Computing 2002: 322-329 |
2001 | ||
22 | EE | Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen: Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. APSEC 2001: 71-78 |
21 | EE | Fong-Ming Shyu, Sao-Jie Chen: A distributed and object-oriented framework for VLSI physical design automation. ISCAS (5) 2001: 77-80 |
20 | EE | Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan: A Three-Stage One-Sided Rearrangeable Polygonal Switching Network. IEEE Trans. Computers 50(11): 1291-1294 (2001) |
2000 | ||
19 | Jih-Ming Fu, Win-Bin See, Pao-Ann Hsiung, Jen-Ming Chao, Sao-Jie Chen: A Java-Based Distributed System Framework for Real-Time Development. ICDCS Workshop on Distributed Real-Time Systems 2000: B31-B36 | |
18 | EE | Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai: Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 735-747 (2000) |
1999 | ||
17 | EE | Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Automatic Router for the Pin Grid Array Package. ASP-DAC 1999: 133-136 |
16 | EE | Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho: An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72 |
15 | EE | Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD 1999: 303-306 |
14 | EE | Chu Yu, Sao-Jie Chen: Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. ISCAS (3) 1999: 524-527 |
13 | Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen: A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. PDPTA 1999: 2982-2987 | |
1998 | ||
12 | EE | Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen: ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. ACM Trans. Design Autom. Electr. Syst. 3(2): 109-135 (1998) |
11 | EE | Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen: NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 182-189 (1998) |
1997 | ||
10 | EE | Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen: Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. TOOLS (24) 1997: 284-293 |
9 | EE | Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen: Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2(2): 135-150 (1997) |
1996 | ||
8 | EE | Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang: PSM: an object-oriented synthesis approach to multiprocessor system design. IEEE Trans. VLSI Syst. 4(1): 83-97 (1996) |
1995 | ||
7 | Jiann-Fu Lin, Sao-Jie Chen: Performance Bounds on Scheduling Parallel Tasks with Setup Time on Hypercube Systems. Informatica (Slovenia) 19(3): (1995) | |
1994 | ||
6 | EE | Chia-Chun Tsai, Sao-Jie Chen: A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10(1): 111-127 (1994) |
1992 | ||
5 | EE | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V alternating router. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 976-991 (1992) |
1991 | ||
4 | EE | Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen: Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. DAC 1991: 60-65 |
1990 | ||
3 | EE | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: Generalized terminal connectivity problem for multilayer layout scheme. Computer-Aided Design 22(7): 423-433 (1990) |
2 | EE | Yu Hen Hu, Sao-Jie Chen: GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 836-845 (1990) |
1 | EE | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990) |