| 2006 |
|---|
| 10 | EE | Tzyy-Kuen Tien,
Jing-Jou Tang,
Kuan-Jou Chen:
A new high speed dynamic PLA.
ISCAS 2006 |
| 2005 |
|---|
| 9 | EE | Li-Chun Tien,
Jing-Jou Tang,
Mi-Chang Chang:
An Automatic Layout Generator for I/O Cells.
IWSOC 2005: 295-300 |
| 1999 |
|---|
| 8 | EE | Jing-Jou Tang:
An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation.
Asian Test Symposium 1999: 81- |
| 7 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999) |
| 1998 |
|---|
| 6 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Wern-Yih Duh:
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation.
Asian Test Symposium 1998: 113-118 |
| 5 | EE | Jing-Jou Tang,
Kuen-Jong Lee,
Bin-Da Liu:
A graph representation for programmable logic arrays to facilitate testing and logic design.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1030-1043 (1998) |
| 1996 |
|---|
| 4 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang,
Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Asian Test Symposium 1996: 100- |
| 3 | EE | Kuen-Jong Lee,
Jing-Jou Tang:
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.
Asian Test Symposium 1996: 165-171 |
| 1995 |
|---|
| 2 | | Jing-Jou Tang,
Bin-Da Liu,
Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs).
ISCAS 1995: 393-396 |
| 1 | EE | Jing-Jou Tang,
Kuen-Jong Lee,
Bin-Da Liu:
A practical current sensing technique for IDDQ testing.
IEEE Trans. VLSI Syst. 3(2): 302-310 (1995) |
