Kuang-Chien Chen

2005
27	EE	Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen: An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107
2004
26	EE	Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen: A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Design & Test of Computers 21(2): 111-120 (2004)
2002
25		Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou: A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154
2001
24	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001)
2000
23	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)
1999
22	EE	Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska: Logic synthesis for engineering change. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 282-292 (1999)
21	EE	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1376-1384 (1999)
1998
20	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637
19	EE	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 852-861 (1998)
1997
18		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng: Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981
17	EE	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Incremental logic rectification. VTS 1997: 143-149
1996
16	EE	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee: Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164
15	EE	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Error Correction Based on Verification Techniques. DAC 1996: 258-261
14	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277-
13	EE	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72
12		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874
1995
11	EE	Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Logic rectification and synthesis for engineering change. ASP-DAC 1995
10	EE	Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng: Logic Synthesis for Engineering Change. DAC 1995: 647-652
9	EE	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen: Cost-free scan: a low-overhead scan path design methodology. ICCAD 1995: 528-533
1994
8	EE	Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen: LUT-based FPGA technology mapping under arbitrary net-delay models. Computers & Graphics 18(4): 507-516 (1994)
1992
7	EE	Kuang-Chien Chen, Masahiro Fujita: Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC 1992: 443-448
6		Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen: An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158
5	EE	Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar: DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers 9(3): 7-20 (1992)
1991
4	EE	Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita: A Resynthesis Approach for Network Optimization. DAC 1991: 458-463
3		Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen: Application of Boolean Unification to Combinational Logic Synthesis. ICCAD 1991: 510-513
2		Kuang-Chien Chen, Masahiro Fujita: Concurrent Resynthesis for Network Optimization. ICCD 1991: 44-48
1990
1	EE	Kuang-Chien Chen, Saburo Muroga: Timing Optimization for Multi-Level Combinational Networks. DAC 1990: 339-344

Coauthor Index

1	Forrest Brewer	[23]
2	Shih-Chieh Chang	[10]
3	David Ihsin Cheng	[11] [18]
4	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[10] [12] [13] [14] [15] [16] [17] [18] [20] [21] [23] [24] [27]
5	Jason Cong	[5] [6] [8]
6	Yuzheng Ding	[5] [6] [8]
7	Masahiro Fujita	[2] [3] [4] [7]
8	Tong Gao	[8]
9	Uwe Gläser	[12]
10	Chung-Yang Huang	[23]
11	Shi-Yu Huang	[12] [13] [14] [15] [16] [17] [18] [20] [21] [23] [24]
12	Madhu K. Iyer	[27]
13	Jing-Yang Jou	[25] [26]
14	Andrew B. Kahng	[5] [6]
15	Yuji Kukimoto	[3]
16	Mike Tien-Chien Lee	[9] [13] [19]
17	Tien-Chien Lee	[16]
18	Chih-Chang Lin	[9] [10] [11] [19] [22]
19	Feng Lu	[27]
20	Juin-Yeu Joseph Lu	[20]
21	Malgorzata Marek-Sadowska	[9] [10] [11] [19] [22]
22	Yusuke Matsunaga	[4]
23	Saburo Muroga	[1] [4]
24	Ganapathy Parthasarathy	[27]
25	Yutaka Tamiya	[3]
26	Peter Trajmar	[5] [6]
27	Li-C. Wang	[27]
28	Chia-Chih Yen	[25] [26]