Chia-Chun Tsai

2008
28	EE	Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao: X-clock routing based on pattern matching. SoCC 2008: 357-360
27	EE	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee: GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Transactions 91-A(1): 365-374 (2008)
2007
26		Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao: An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. IMECS 2007: 346-351
25	EE	Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee: Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Transactions 90-A(3): 651-658 (2007)
2006
24	EE	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao: Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS 2006: 1285-1288
23	EE	Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee: Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS 2006: 812-815
22	EE	Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai: Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. ICICIC (2) 2006: 515-518
21	EE	Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao: A single chip image sensor embedded smooth spatial filter with A/D conversion. ISCAS 2006
20	EE	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao: Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS 2006
19	EE	Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai: Inductance extraction for general interconnect structures. ISCAS 2006
18	EE	Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu: Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22(6): 1585-1599 (2006)
2005
17	EE	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee: Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) 2005: 561-566
16	EE	Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang: A new low-power turbo decoder using HDA-DHDD stopping iteration. ISCAS (2) 2005: 1040-1043
15	EE	Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen: A new CCII-based pipelined analog to digital converter. ISCAS (6) 2005: 6170-6173
2004
14	EE	Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang: RCGES: Retargetable Code Generation for Embedded Systems. ATVA 2004: 415-425
2000
13	EE	Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai: Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 735-747 (2000)
1999
12	EE	Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Automatic Router for the Pin Grid Array Package. ASP-DAC 1999: 133-136
11	EE	Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho: An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72
10	EE	Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai: An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD 1999: 303-306
1998
9	EE	Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen: NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 182-189 (1998)
1997
8	EE	Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen: Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2(2): 135-150 (1997)
1996
7	EE	Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng: Performance driven bus buffer insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 429-437 (1996)
1995
6	EE	Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995
1994
5	EE	Chia-Chun Tsai, Sao-Jie Chen: A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10(1): 111-127 (1994)
1992
4	EE	Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V alternating router. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 976-991 (1992)
1991
3	EE	Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng: A knowledge-based program for compacting mask layout of integrated circuits. Computer-Aided Design 23(3): 223-231 (1991)
1990
2	EE	Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: Generalized terminal connectivity problem for multilayer layout scheme. Computer-Aided Design 22(7): 423-433 (1990)
1	EE	Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng: An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990)

Coauthor Index

1	Yao-Wen Chang	[19]
2	Jiann-Jong Chen	[15]
3	Jong-Jang Chen	[10] [12]
4	S. F. Steven Chen	[3]
5	Sao-Jie Chen	[1] [2] [4] [5] [8] [9] [10] [11] [12] [13]
6	Shuenn-Shi Chen	[10] [12]
7	Chung-Kuan Cheng	[6] [7]
8	Yu-Min Cheng	[26]
9	Jong-Sheng Cherng	[11]
10	Huang-Chi Chou	[21]
11	Yang-Hsin Fan	[14] [22] [26]
12	Wu-Shiung Feng	[1] [2] [3] [4]
13	Jan-Ming Ho	[8] [11] [13]
14	Pei-Yung Hsiao	[3]
15	Rong-Shue Hsiao	[20] [21] [24] [26] [28]
16	Hann-Cheng Huang	[18]
17	Yuh-Shyan Hwang	[14] [15] [16]
18	Shyh-Kang Jeng	[19]
19	Chien-Wen Kao	[20]
20	De-Yu Kao	[6] [7]
21	Chung-Chieh Kuo	[17] [23] [25] [28]
22	Chun-Ying Lai	[19]
23	Trong-Yen Lee	[14] [15] [16] [17] [18] [20] [21] [22] [23] [24] [25] [26] [27] [28]
24	Wen-Ta Lee	[14] [15] [16] [17] [18]
25	Lu-Po Liao	[15]
26	San-Ho Lin	[16]
27	Ting-Ting Y. Lin	[6]
28	Yu-Ting Shieh	[23]
29	Chwan-Ming Wang	[9]
30	Jan-Ou Wu	[17] [18] [20] [23] [24] [25] [27] [28]
31	Cheng-Hsing Yang	[8] [13]
32	Tsung-Hsun Yang	[14]