| 1999 |
|---|
| 9 | | Pierre-Yves Calland,
Jack Dongarra,
Yves Robert:
Tiling on systems with communication/computation overlap.
Concurrency - Practice and Experience 11(3): 139-153 (1999) |
| 1998 |
|---|
| 8 | EE | Pierre-Yves Calland,
Alain Darte,
Yves Robert:
Circuit Retiming Applied to Decomposed Software Pipelining.
IEEE Trans. Parallel Distrib. Syst. 9(1): 24-35 (1998) |
| 7 | EE | Pierre-Yves Calland,
Anne Mignotte,
Olivier Peyran,
Yves Robert,
Frédéric Vivien:
Retiming DAGs [direct acyclic graph].
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1319-1325 (1998) |
| 6 | | Pierre-Yves Calland,
Alain Darte,
Yves Robert,
Frédéric Vivien:
On the Removal of Anti- and Output-Dependences.
International Journal of Parallel Programming 26(2): 285-312 (1998) |
| 1997 |
|---|
| 5 | EE | Pierre-Yves Calland,
Jack Dongarra,
Yves Robert:
Tiling with limited resources.
ASAP 1997: 229-238 |
| 4 | | Pierre-Yves Calland,
Alain Darte,
Yves Robert,
Frédéric Vivien:
Plugging Anti and Output Dependence Removal Techniques Into Loop Parallelization Algorithm.
Parallel Computing 23(1-2): 251-266 (1997) |
| 1996 |
|---|
| 3 | EE | Pierre-Yves Calland,
Alain Darte,
Yves Robert,
Frédéric Vivien:
On the Removal of Anti and Output Dependences.
ASAP 1996: 353-364 |
| 2 | EE | Pierre-Yves Calland,
Alain Darte,
Yves Robert:
A New Guaranteed Heuristic for the Software Pipelining Problem.
International Conference on Supercomputing 1996: 261-269 |
| 1995 |
|---|
| 1 | EE | Pierre-Yves Calland,
Tanguy Risset:
Precise Tiling for Uniform Loop Nests.
ASAP 1995: 330- |
