| 2001 |
|---|
| 5 | EE | Rony Kay,
Rob A. Rutenbar:
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 672-679 (2001) |
| 2000 |
|---|
| 4 | EE | Rony Kay,
Rob A. Rutenbar:
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.
ISPD 2000: 61-68 |
| 1998 |
|---|
| 3 | EE | Rony Kay,
Lawrence T. Pileggi:
PRIMO: Probability Interpretation of Moments for Delay Calculation.
DAC 1998: 463-468 |
| 2 | EE | Rony Kay,
Lawrence T. Pileggi:
EWA: efficient wiring-sizing algorithm for signal nets and clock nets.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 40-49 (1998) |
| 1997 |
|---|
| 1 | EE | Rony Kay,
Gennady Bucheuv,
Lawrence T. Pileggi:
EWA: exact wiring-sizing algorithm.
ISPD 1997: 178-185 |
