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A. R. Naseer

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2007
8EEIsmat K. Maarouf, A. R. Naseer: WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs. AICCSA 2007: 258-265
2006
7EEIsmat K. Maarouf, A. R. Naseer: SNARE: sensor node attached reputation evaluator. CoNEXT 2006: 29
1998
6EEA. R. Naseer, M. Balakrishnan, Anshul Kumar: Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 624-631 (1998)
1997
5EEA. R. Naseer, M. Balakrishnan, Anshul Kumar: Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139
1995
4 A. R. Naseer, M. Balakrishnan, Anshul Kumar: Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148
1994
3 A. R. Naseer, M. Balakrishnan, Anshul Kumar: An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110
2 A. R. Naseer, M. Balakrishnan, Anshul Kumar: FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24
1993
1 C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer: High Level Design Experiences with IDEAS. VLSI Design 1993: 110

Coauthor Index

1C. S. Ajay [1]
2M. Balakrishnan [1] [2] [3] [4] [5] [6]
3D. Harikrishna [1]
4M. Karunakaran [1]
5Anshul Kumar [1] [2] [3] [4] [5] [6]
6Shashi Kumar [1]
7Ismat K. Maarouf [7] [8]
8V. Mudgil [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)