Brian T. Murray

2005
20	EE	Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. IEEE Trans. Parallel Distrib. Syst. 16(3): 258-270 (2005)
2003
19	EE	Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray: Low-Cost On-Line Fault Detection Using Control Flow Assertions. IOLTS 2003: 137-143
18	EE	Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Dependable Communication Synthesis for Distributed Embedded Systems. SAFECOMP 2003: 275-288
2002
17	EE	Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Time-Constrained Failure Diagnosis in Distributed Embedded Systems. DSN 2002: 449-458
2000
16	EE	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. VLSI Syst. 8(5): 633-636 (2000)
1999
15	EE	Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. SRDS 1999: 212-221
14	EE	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27
13	EE	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electronic Testing 15(1-2): 97-114 (1999)
1998
12	EE	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423
11	EE	Hussain Al-Asaad, Brian T. Murray, John P. Hayes: Online BIST for Embedded Systems. IEEE Design & Test of Computers 15(4): 17-24 (1998)
10		Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes: Optimal Zero-Aliasing Space Compaction of Test Responses. IEEE Trans. Computers 47(11): 1171-1187 (1998)
9	EE	Krishnendu Chakrabarty, Brian T. Murray: Design of built-in test generator circuits using width compression. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1044-1051 (1998)
8	EE	Hussain Al-Asaad, John P. Hayes, Brian T. Murray: Scalable Test Generators for High-Speed Datapath Circuits. J. Electronic Testing 12(1-2): 111-125 (1998)
1997
7		Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray: Test Width Compression for Built-In Self Testing. ITC 1997: 328-337
1996
6		Brian T. Murray, John P. Hayes: Testing ICs: Getting to the Core of the Problem. IEEE Computer 29(11): 32-38 (1996)
1995
5		Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes: Optimal Space Compaction of Test Responses. ITC 1995: 834-843
1991
4		Brian T. Murray, John P. Hayes: Test Propagation Through Modules and Circuits. ITC 1991: 748-757
1990
3	EE	Brian T. Murray, John P. Hayes: Hierarchical test generation using precomputed tests for modules. IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 594-603 (1990)
1989
2		Debashis Bhattacharya, Brian T. Murray, John P. Hayes: High-Level Test Generation for VLSI. IEEE Computer 22(4): 16-24 (1989)
1988
1		Brian T. Murray, John P. Hayes: Hierarchical Test Generation Using Precomputed Tests for Modules. ITC 1988: 221-229

Coauthor Index

1	Hussain Al-Asaad	[8] [11]
2	Debashis Bhattacharya	[2]
3	Krishnendu Chakrabarty	[5] [7] [9] [10] [12] [13] [14] [16]
4	John P. Hayes	[1] [2] [3] [4] [5] [6] [8] [10] [11] [15] [17] [18] [19] [20]
5	Vikram Iyengar	[12] [13] [14] [16]
6	Nagarajan Kandasamy	[15] [17] [18] [20]
7	Jian Liu	[7]
8	Rajesh Venkatasubramanian	[19]
9	Minyao Zhu	[7]