| 2001 |
|---|
| 24 | EE | Tobias Schüle,
Albrecht P. Stroele:
Scheduling tests for low power built-in self-test.
ISCAS (5) 2001: 247-250 |
| 23 | EE | Tobias Schüle,
Albrecht P. Stroele:
Test Scheduling for Minimal Energy Consumption under Power Constraints.
VTS 2001: 312-318 |
| 2000 |
|---|
| 22 | EE | Frank Mayer,
Albrecht P. Stroele:
A Versatile BIST Technique Combining Test Registers and Accumulators.
VLSI Design 2000: 412- |
| 21 | EE | Albrecht P. Stroele:
Synthesis for Arithmetic Built-In Self-Tes.
VTS 2000: 165-170 |
| 20 | EE | Albrecht P. Stroele,
Steffen Tarnick:
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes.
J. Electronic Testing 16(4): 355-367 (2000) |
| 1999 |
|---|
| 19 | EE | Albrecht P. Stroele,
Frank Mayer:
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.
Asian Test Symposium 1999: 101-106 |
| 18 | EE | Albrecht P. Stroele,
Steffen Tarnick:
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.
VTS 1999: 361-369 |
| 1998 |
|---|
| 17 | EE | Frank Mayer,
Albrecht P. Stroele:
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit.
Asian Test Symposium 1998: 15-20 |
| 16 | EE | Steffen Tarnick,
Albrecht P. Stroele:
Embedded self-testing checkers for low-cost arithmetic codes.
ITC 1998: 514-523 |
| 15 | EE | Albrecht P. Stroele:
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions.
VTS 1998: 78-85 |
| 14 | EE | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Hardware-optimal test register insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 531-539 (1998) |
| 1997 |
|---|
| 13 | EE | Albrecht P. Stroele,
Frank Mayer:
Methods to reduce test application time for accumulator-based self-test.
VTS 1997: 48-53 |
| 12 | EE | Albrecht P. Stroele:
BIST Pattern Generators Using Addition and Subtraction Operations.
J. Electronic Testing 11(1): 69-80 (1997) |
| 1996 |
|---|
| 11 | EE | Albrecht P. Stroele:
Arithmetic Pattern Generators for Built-In Self-Test.
ICCD 1996: 131-134 |
| 10 | EE | Albrecht P. Stroele:
Test response compaction using arithmetic functions.
VTS 1996: 380-386 |
| 1995 |
|---|
| 9 | EE | Gerald Spiegel,
Albrecht P. Stroele:
A unified approach to the extraction of realistic multiple bridging and break faults.
EURO-DAC 1995: 184-189 |
| 8 | EE | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Test register insertion with minimum hardware cost.
ICCAD 1995: 95-101 |
| 7 | | Albrecht P. Stroele:
A Self-Test Approach Using Accumulators as Test Pattern Generators.
ISCAS 1995: 2120-2123 |
| 6 | EE | Albrecht P. Stroele:
Signature analysis and aliasing for sequential circuits.
VTS 1995: 118-124 |
| 1994 |
|---|
| 5 | | Albrecht P. Stroele:
Signature Analysis for Sequential Circuits with Reset.
EDAC-ETC-EUROASIC 1994: 113-118 |
| 4 | | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Configuring Flip-Flops to BIST Registers.
ITC 1994: 939-948 |
| 1993 |
|---|
| 3 | | Albrecht P. Stroele:
Partitioning and hierarchical description of self-testable designs.
VLSI 1993: 113-122 |
| 1992 |
|---|
| 2 | | Albrecht P. Stroele:
Self-Test Scheduling with Bounded Test Execution.
ITC 1992: 130-139 |
| 1991 |
|---|
| 1 | | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Signature Analysis and Test Scheduling for Self-Testable Circuits.
FTCS 1991: 96-103 |
