| |
| 1998 | ||
|---|---|---|
| 7 | EE | Chih-Ang Chen, Sandeep K. Gupta: Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 692-705 (1998) |
| 1996 | ||
| 6 | EE | Chih-Ang Chen, Sandeep K. Gupta: A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. DAC 1996: 209-214 |
| 5 | Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. IEEE Trans. Computers 45(3): 257-269 (1996) | |
| 4 | EE | Chih-Ang Chen, Sandeep K. Gupta: Design of efficient BIST test pattern generators for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1568-1575 (1996) |
| 1995 | ||
| 3 | Chih-Ang Chen, Sandeep K. Gupta: A Methodology to Design Efficient BIST Test Pattern Generators. ITC 1995: 814-823 | |
| 1994 | ||
| 2 | Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Stuck-Open and Delay Testing. EDAC-ETC-EUROASIC 1994: 289-296 | |
| 1 | EE | Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain: Low power state assignment targeting two-and multi-level logic implementations. ICCAD 1994: 82-87 |
| 1 | Alvin M. Despain | [1] |
| 2 | Sandeep K. Gupta | [2] [3] [4] [5] [6] [7] |
| 3 | Massoud Pedram | [1] |
| 4 | Chi-Ying Tsui | [1] |