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Keikichi Tamaru

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2000
19EETomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru: A method for linking process-level variability to system performances. ASP-DAC 2000: 547-552
1999
18EEMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451
1998
17EEAkio Hirata, Hidetoshi Onodera, Keikichi Tamaru: Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544
16EEMasanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226
15EEMasaki Kondo, Hidetoshi Onodera, Keikichi Tamaru: Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 400-405 (1998)
14EEVasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru: A memory efficient array architecture for real-time motion estimation. Systems and Computers in Japan 29(9): 13-20 (1998)
1997
13EEVasily G. Moshnyaga, Keikichi Tamaru: A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32
1996
12EEGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154-
1995
11EEMasaki Kondo, Hidetoshi Onodera, Keikichi Tamaru: A model-adaptable MOSFET parameter extraction system. ASP-DAC 1995
10EEVasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru: A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995
9EEGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427
8 Kuei-Ming Lu, Keikichi Tamaru: A New Algorithm for Sorting Problem with Reformed CAM. ISCAS 1995: 1045-1048
7 Vasily G. Moshnyaga, Keikichi Tamaru: A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563
6EEFarhad Fuad Islam, Keikichi Tamaru: High speed merged array multiplication. VLSI Signal Processing 10(1): 41-52 (1995)
1993
5EEVasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru: Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103
4 Farhad Fuad Islam, Keikichi Tamaru: An Architecture for Intermediate Area-time Complexity Multiplier. ISCAS 1993: 1825-1828
1992
3 Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192
1991
2EEHidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru: Branch-and-Bound Placement for Building Block Layout. DAC 1991: 433-439
1990
1 M. Ohmura, Hiroto Yasuura, Keikichi Tamaru: Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179

Coauthor Index

1Guangqiu Chen [9] [12]
2Hiroaki Fujita [19]
3Tomohiro Fujita [19]
4Masanori Hashimoto [16] [18]
5Akio Hirata [17]
6Farhad Fuad Islam [4] [6]
7Masaki Kondo [11] [15]
8Kuei-Ming Lu [8]
9Hiroshi Mori [5]
10Vasily G. Moshnyaga [3] [5] [7] [10] [13] [14]
11Fumiaki Ohbayashi [10]
12M. Ohmura [1]
13Ken-ichi Okada [19]
14Hidetoshi Onodera [2] [5] [9] [11] [12] [15] [16] [17] [18] [19]
15Yo Taniguchi [2]
16Naoto Watanabe [14]
17Hiroto Yasuura [1] [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)