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Abhijit Ghosh

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2000
26EELuc Séméria, Abhijit Ghosh: Methodology for hardware/software co-verification in C/C++ (short paper). ASP-DAC 2000: 405-408
25EEVivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh: YAML: A Tool for Hardware Design Visualization and Capture. ISSS 2000: 9-17
24EEAbhijit Ghosh, Ranga Vemuri: Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design 2000: 84-
1999
23EEAbhijit Ghosh, Joachim Kunkel, Stan Y. Liao: Hardware Synthesis from C/C++. DATE 1999: 387-389
22EEAbhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri: Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI 1999: 140-143
21EEAbhijit Ghosh, Ranga Vemuri: Formal Verification of Synthesized Analog Designs. ICCD 1999: 40-45
1998
20EEFuchun Joseph Lin, Hong Liu, Abhijit Ghosh: A Methodology for Feature Interaction Detection in the AIN 0.1 Framework. IEEE Trans. Software Eng. 24(10): 797-817 (1998)
19EEJosé C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 279-284 (1998)
1997
18EEJosé C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White: Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997)
1996
17EESrinivas Devadas, Abhijit Ghosh, Kurt Keutzer: An observability-based code coverage metric for functional simulation. ICCAD 1996: 418-425
1995
16EEJosé Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh: Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444
15EEAmelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic manipulation of Boolean functions using free Boolean diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 87-95 (1995)
1994
14EEMazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81
13EEMazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994)
1993
12EEJosé C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Retiming sequential circuits for low power. ICCAD 1993: 398-402
11EEAmelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic construction and manipulation of free Boolean diagrams. ICCAD 1993: 544-583
10EEStan Y. Liao, Srinivas Devadas, Abhijit Ghosh: Boolean factorization using multiple-valued minimization. ICCAD 1993: 606-611
9EEAbhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 579-598 (1993)
1992
8EEAbhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White: Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC 1992: 253-259
7EEAmelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer: On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD 1992: 402-407
6EEAbhijit Ghosh, Srinivas Devadas, A. Richard Newton: Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1166-1172 (1992)
1991
5 Pranav Ashar, Abhijit Ghosh, Srinivas Devadas: Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264
4EEAbhijit Ghosh, Srinivas Devadas, A. Richard Newton: Test generation and verification for highly sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 652-667 (1991)
1990
3EEAbhijit Ghosh, Srinivas Devadas, A. Richard Newton: Verification of Interacting Sequential Circuits. DAC 1990: 213-219
2EEAbhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential Test Generation at the Register-Transfer and Logic Levels. DAC 1990: 580-586
1 Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87

Coauthor Index

1Mazhar Alidina [13] [14]
2Pranav Ashar [1] [5]
3Srinivas Devadas [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
4Frederic Doucet [25]
5Rajesh K. Gupta (Rajesh Gupta) [25]
6Kurt Keutzer [7] [8] [17] [18]
7Joachim Kunkel [23]
8Stan Y. Liao [10] [23] [25]
9Fuchun Joseph Lin [20]
10Hong Liu [20]
11Sandeep K. Lodha [22]
12José C. Monteiro (José Monteiro) [12] [13] [14] [16] [18] [19]
13A. Richard Newton [1] [2] [3] [4] [6] [9]
14Marios C. Papaefthymiou [13] [14]
15John Rinderknecht [16]
16Luc Séméria [26]
17Amelia Shen [7] [11] [15]
18Vivek Sinha [25]
19Chuck Siska [25]
20Ranga Vemuri [21] [22] [24]
21Jacob K. White (Jacob White) [8] [18]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)