| 2003 |
|---|
| 11 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan:
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
IEEE Trans. Computers 52(12): 1543-1558 (2003) |
| 2000 |
|---|
| 10 | EE | Mitrajit Chatterjee,
Savita Banerjee,
Dhiraj K. Pradhan:
Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers 49(1): 16-32 (2000) |
| 9 | EE | Debjyoti Paul,
Mitrajit Chatterjee,
Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000) |
| 1999 |
|---|
| 8 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee:
GLFSR-a new test pattern generator for built-in-self-test.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 238-247 (1999) |
| 1998 |
|---|
| 7 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan,
Wolfgang Kunz:
LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998) |
| 1996 |
|---|
| 6 | EE | Dhiraj K. Pradhan,
Debjyoti Paul,
Mitrajit Chatterjee:
VERILAT: verification using logic augmentation and transformations.
ICCAD 1996: 88-95 |
| 5 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee,
Madhu V. Swarna,
Wolfgang Kunz:
Gate-level synthesis for low-power using new transformations.
ISLPED 1996: 297-300 |
| 1995 |
|---|
| 4 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan,
Wolfgang Kunz:
LOT: logic optimization with testability-new transformations using recursive learning.
ICCAD 1995: 318-325 |
| 3 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan:
A novel pattern generator for near-perfect fault-coverage.
VTS 1995: 417-425 |
| 1994 |
|---|
| 2 | | Dhiraj K. Pradhan,
Mitrajit Chatterjee:
GLFSR - A New Test Pattern Generator for Built-In Self-Test.
ITC 1994: 481-490 |
| 1993 |
|---|
| 1 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee,
Savita Banerjee:
Buffer assignment for data driven architectures.
ICCAD 1993: 665-668 |
