Daniel Brand

2008
32	EE	Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards: Flexible pointer analysis using assign-fetch graphs. SAC 2008: 234-239
2007
31	EE	Daniel Brand, Marcio Buss, Vugranam C. Sreedhar: Evidence-Based Analysis and Inferring Preconditions for Bug Detection. ICSM 2007: 44-53
2002
30	EE	John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
2000
29	EE	Daniel Brand: A Software Falsifier. ISSRE 2000: 174-185
28	EE	John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A system for production logic synthesis. IBM Journal of Research and Development 44(1): 157-166 (2000)
1998
27	EE	Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Don't cares in synthesis: theoretical pitfalls and practical solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 285-304 (1998)
1996
26	EE	Daniel Brand, Chandramouli Visweswariah: Inaccuracies in power estimation during logic synthesis. ICCAD 1996: 388-394
25		Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler: BooleDozer: Logic synthesis for ASICs. IBM Journal of Research and Development 40(4): 407-430 (1996)
1995
24	EE	Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash: Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278
23	EE	Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Be careful with don't cares. ICCAD 1995: 83-86
1994
22	EE	Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain: Incremental synthesis. ICCAD 1994: 14-18
21		Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm: In the Driver's Seat of BooleDozer. ICCD 1994: 518-521
20	EE	Daniel Brand, Vijay S. Iyengar: Identification of redundant delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 553-565 (1994)
1993
19	EE	Daniel Brand: Verification of large synthesized designs. ICCAD 1993: 534-537
18		Daniel Brand, Tsutomu Sasao: Minimization of AND-EXOR Expressions Using Rewrite Rules. IEEE Trans. Computers 42(5): 568-576 (1993)
17	EE	Daniel Brand: Exhaustive simulation need not require an exponential number of tests. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1635-1641 (1993)
1992
16	EE	Daniel Brand: Exhaustive simulation need not require an exponential number of tests. ICCAD 1992: 98-101
15		Daniel Brand, Vijay S. Iyengar: Identification of Single Gate Delay Fault Redundancies. ICCD 1992: 24-28
1989
14		Daniel Brand, Vijay S. Iyengar: Synthesis of Pseudo-Random Pattern Testable Designs. ITC 1989: 501-508
1988
13		Daniel Brand, Vijay S. Iyengar: Timing Analysis Using Functional Analysis. IEEE Trans. Computers 37(10): 1309-1315 (1988)
1986
12	EE	William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen: Technology adaption in logic synthesis. DAC 1986: 94-100
11		Daniel Brand: Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 35(3): 274-278 (1986)
1985
10	EE	John A. Darringer, Daniel Brand, William H. Joyner Jr., Louise Trevillyan, John V. Gerbi: Production logic synthesis. ACM Conference on Computer Science 1985: 13-16
1984
9		John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A System for Production Logic Synthesis. IBM Journal of Research and Development 28(5): 537-545 (1984)
1983
8		Daniel Brand: Redundancy and Don't Cares in Logic Synthesis. IEEE Trans. Computers 32(10): 947-952 (1983)
7	EE	Daniel Brand, Pitro Zafiropulo: On Communicating Finite-State Machines J. ACM 30(2): 323-342 (1983)
1978
6		William H. Joyner Jr., William C. Carter, Daniel Brand: Using Machine Descriptions in Program Verification. Jerusalem Conference on Information Technology 1978: 515-522
5		Daniel Brand, William H. Joyner Jr.: Verification of Protocols Using Symbolic Execution. Computer Networks 2: 351-360 (1978)
4	EE	Daniel Brand: Path Calculus in Program Verification. J. ACM 25(4): 630-651 (1978)
1976
3		Daniel Brand: Proving Programs Incorrect. ICALP 1976: 201-227
2		Daniel Brand: Analytic Resolution in Theorem Proving. Artif. Intell. 7(4): 285-318 (1976)
1975
1		Daniel Brand: Proving Theorems with the Modification Method. SIAM J. Comput. 4(4): 412-430 (1975)

Coauthor Index

1	Reinaldo A. Bergamaschi	[23] [24] [27] [30]
2	Michel R. C. M. Berkelaar	[24]
3	Subhrajit Bhattacharya	[30]
4	Marcio Buss	[31] [32]
5	William C. Carter	[6]
6	Han Hsun Chao	[25]
7	Robert F. Damiano	[21]
8	John A. Darringer	[9] [10] [28] [30]
9	Anthony D. Drumm	[21] [22] [25]
10	Stephen A. Edwards	[32]
11	David J. Geiger	[25]
12	John V. Gerbi	[9] [10] [28]
13	Lukas P. P. P. van Ginneken	[21]
14	Steven C. Gundersen	[12]
15	Andreas Herkersdorf	[30]
16	Nathaniel Hieter	[25]
17	Vijay S. Iyengar	[13] [14] [15] [20]
18	William H. Joyner Jr.	[5] [6] [9] [10] [12] [28]
19	Sandip Kundu	[22]
20	David S. Kung	[25]
21	Joseph K. Morrell	[30]
22	Indira Nair	[30]
23	Prakash Narain	[22]
24	Theresa A. Nix	[12]
25	Peter J. Osler	[25]
26	S. Prakash	[24]
27	Lakshmi N. Reddy	[25]
28	Patricia Sagmeister	[30]
29	Tsutomu Sasao	[18]
30	Youngsoo Shin	[30]
31	Vugranam C. Sreedhar	[31] [32]
32	Leon Stok	[23] [24] [25] [27]
33	Andrew J. Sullivan	[25]
34	Louise Trevillyan	[9] [10] [12] [28]
35	Chandramouli Visweswariah	[26]
36	Pitro Zafiropulo	[7]

Colors in the list of coauthors