Mineo Kaneko

2009
19	EE	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI 2009: 27-32
2008
18	EE	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Safe clocking register assignment in datapath synthesis. ICCD 2008: 120-127
17	EE	Takanuki Obata, Mineo Kaneko: Concurrent skew and control step assignments in RT-level datapath synthesis. ISCAS 2008: 2018-2021
16	EE	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Transactions 91-A(4): 1044-1053 (2008)
2007
15	EE	Koji Ohashi, Mineo Kaneko: Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ACM Great Lakes Symposium on VLSI 2007: 481-484
14	EE	Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara: Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423
13	EE	Koji Ohashi, Mineo Kaneko: Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems. IEICE Transactions 90-A(3): 659-669 (2007)
2006
12	EE	Mineo Kaneko: Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. APCCAS 2006: 335-338
2005
11	EE	Koji Ohashi, Mineo Kaneko: Statistical Analysis Driven Synthesis of Asynchronous Systems. ICCD 2005: 200-205
10	EE	Koji Ohashi, Mineo Kaneko: Statistical schedule length analysis in asynchronous datapath synthesis. ISCAS (1) 2005: 700-703
2003
9	EE	Mineo Kaneko, Kazuaki Oshio: Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. ISCAS (5) 2003: 645-648
2000
8	EE	Koji Ohashi, Mineo Kaneko, Satoshi Tayu: Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. ICCD 2000: 370-
7	EE	Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko: An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. ISPAN 2000: 114-120
1998
6	EE	Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 60-68 (1998)
1997
5	EE	Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31
1994
4		Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko: AR Spectrum Estimation Based on Wavelet Representation. ISCAS 1994: 625-628
3		Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda: A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. ISCAS 1994: 67-70
2		Mineo Kaneko, Kazuhiro Sakaguchi: Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. ISCAS 1994: 93-96
1993
1		Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi: A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. ISCAS 1993: 2094-2097

Coauthor Index

1	Hideo Fujiwara	[14]
2	Kunihiro Fujiyoshi	[5] [6]
3	Tomohiro Hayashi	[1]
4	Keisuke Inoue	[16] [18] [19]
5	Tsuyoshi Iwagaki	[14] [16] [18] [19]
6	Motoyasu Katsura	[7]
7	Masahiro Masuda	[1]
8	Hiroshi Murata	[5] [6]
9	Takanuki Obata	[17]
10	Koji Ohashi	[8] [10] [11] [13] [15]
11	Satoshi Ohtake	[14]
12	Mahoki Onoda	[3]
13	Kazuaki Oshio	[9]
14	Fernando Gil Resende	[4]
15	Kazuhiro Sakaguchi	[2]
16	Sarwono Sutikno	[3]
17	Satoshi Tayu	[7] [8]
18	Keiichi Tokuda	[4]

Colors in the list of coauthors