Mineo Kaneko

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19EEKeisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI 2009: 27-32
18EEKeisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Safe clocking register assignment in datapath synthesis. ICCD 2008: 120-127
17EETakanuki Obata, Mineo Kaneko: Concurrent skew and control step assignments in RT-level datapath synthesis. ISCAS 2008: 2018-2021
16EEKeisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki: Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Transactions 91-A(4): 1044-1053 (2008)
15EEKoji Ohashi, Mineo Kaneko: Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ACM Great Lakes Symposium on VLSI 2007: 481-484
14EETsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara: Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423
13EEKoji Ohashi, Mineo Kaneko: Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems. IEICE Transactions 90-A(3): 659-669 (2007)
12EEMineo Kaneko: Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. APCCAS 2006: 335-338
11EEKoji Ohashi, Mineo Kaneko: Statistical Analysis Driven Synthesis of Asynchronous Systems. ICCD 2005: 200-205
10EEKoji Ohashi, Mineo Kaneko: Statistical schedule length analysis in asynchronous datapath synthesis. ISCAS (1) 2005: 700-703
9EEMineo Kaneko, Kazuaki Oshio: Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. ISCAS (5) 2003: 645-648
8EEKoji Ohashi, Mineo Kaneko, Satoshi Tayu: Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. ICCD 2000: 370-
7EESatoshi Tayu, Motoyasu Katsura, Mineo Kaneko: An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. ISPAN 2000: 114-120
6EEHiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 60-68 (1998)
5EEHiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko: VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31
4 Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko: AR Spectrum Estimation Based on Wavelet Representation. ISCAS 1994: 625-628
3 Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda: A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. ISCAS 1994: 67-70
2 Mineo Kaneko, Kazuhiro Sakaguchi: Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. ISCAS 1994: 93-96
1 Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi: A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. ISCAS 1993: 2094-2097

Coauthor Index

1Hideo Fujiwara [14]
2Kunihiro Fujiyoshi [5] [6]
3Tomohiro Hayashi [1]
4Keisuke Inoue [16] [18] [19]
5Tsuyoshi Iwagaki [14] [16] [18] [19]
6Motoyasu Katsura [7]
7Masahiro Masuda [1]
8Hiroshi Murata [5] [6]
9Takanuki Obata [17]
10Koji Ohashi [8] [10] [11] [13] [15]
11Satoshi Ohtake [14]
12Mahoki Onoda [3]
13Kazuaki Oshio [9]
14Fernando Gil Resende [4]
15Kazuhiro Sakaguchi [2]
16Sarwono Sutikno [3]
17Satoshi Tayu [7] [8]
18Keiichi Tokuda [4]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)