2004 |
11 | EE | Rahul M. Rao,
Jeffrey L. Burns,
Richard B. Brown:
Analysis and Optimization of Enhanced MTCMOS Scheme.
VLSI Design 2004: 234-239 |
2003 |
10 | EE | Rahul M. Rao,
Frank Liu,
Jeffrey L. Burns,
Richard B. Brown:
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.
ICCAD 2003: 689-692 |
9 | EE | Rahul M. Rao,
Jeffrey L. Burns,
Anirudh Devgan,
Richard B. Brown:
Efficient techniques for gate leakage estimation.
ISLPED 2003: 100-103 |
8 | EE | Juan Antonio Carballo,
Jeffrey L. Burns,
Seung-Moon Yoo,
Ivan Vo,
V. Robert Norman:
A semi-custom voltage-island technique and its application to high-speed serial links.
ISLPED 2003: 60-65 |
7 | EE | Emrah Acar,
Anirudh Devgan,
Rahul M. Rao,
Ying Liu,
Haihua Su,
Sani R. Nassif,
Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits.
ISLPED 2003: 96-99 |
1999 |
6 | | Tai-Hung Liu,
Malay K. Ganai,
Adnan Aziz,
Jeffrey L. Burns:
Performance Driven Synthesis for Pass-Transistor Logic.
VLSI Design 1999: 372-377 |
1998 |
5 | EE | Jeffrey L. Burns,
Jack A. Feldman:
C5M-a control-logic layout synthesis system for high-performance microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 14-23 (1998) |
1997 |
4 | EE | Jeffrey L. Burns,
Jack A. Feldman:
C5M - a control logic layout synthesis system for high-performance microprocessors.
ISPD 1997: 110-115 |
1994 |
3 | | Venkat K. R. Chiluvuri,
Israel Koren,
Jeffrey L. Burns:
The Effect of Wire Length Minimization on Yield.
DFT 1994: 97-105 |
1988 |
2 | EE | Douglas Braun,
Jeffrey L. Burns,
Fabio Romeo,
Alberto L. Sangiovanni-Vincentelli,
Kartikeya Mayaram,
Srinivas Devadas,
Hi-Keung Tony Ma:
Techniques for multilayer channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 698-712 (1988) |
1986 |
1 | EE | Douglas Braun,
Jeffrey L. Burns,
Srinivas Devadas,
Hi-Keung Tony Ma,
Kartikeya Mayaram,
Fabio Romeo,
Alberto L. Sangiovanni-Vincentelli:
Chameleon: a new multi-layer channel router.
DAC 1986: 495-502 |