Shih-Arn Hwang

List of publications from the DBLP Bibliography Server - FAQ

2001

3 EE Shih-Arn Hwang, Cheng-Wen Wu: Unified VLSI systolic array design for LZ data compression. IEEE Trans. VLSI Syst. 9(4): 489-499 (2001)

1999

2 EE Shih-Arn Hwang, Cheng-Wen Wu: Test Energy Minimization for C-Testable ILAs. J. Inf. Sci. Eng. 15(6): 899-911 (1999)

1998

1 EE Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu: Sequential circuit fault simulation using logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 724-736 (1998)

2001
3	EE	Shih-Arn Hwang, Cheng-Wen Wu: Unified VLSI systolic array design for LZ data compression. IEEE Trans. VLSI Syst. 9(4): 489-499 (2001)
1999
2	EE	Shih-Arn Hwang, Cheng-Wen Wu: Test Energy Minimization for C-Testable ILAs. J. Inf. Sci. Eng. 15(6): 899-911 (1999)
1998
1	EE	Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu: Sequential circuit fault simulation using logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 724-736 (1998)

Coauthor Index