Harsha Sathyamurthy

List of publications from the DBLP Bibliography Server - FAQ

1998

2 EE Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 173-182 (1998)

1995

1 EE Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470

1998
2	EE	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 173-182 (1998)
1995
1	EE	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470

Coauthor Index