| |
| 1998 | ||
|---|---|---|
| 3 | EE | Kerry S. Lowe, P. Glenn Gulak: A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 419-434 (1998) |
| 1994 | ||
| 2 | EE | Kerry S. Lowe, P. Glenn Gulak: A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. EURO-DAC 1994: 42-47 |
| 1993 | ||
| 1 | EE | Kerry S. Lowe, P. Glenn Gulak: Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. ICCAD 1993: 216-219 |
| 1 | P. Glenn Gulak | [1] [2] [3] |