| |
| 1998 | ||
|---|---|---|
| 5 | EE | Jeffrey L. Burns, Jack A. Feldman: C5M-a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 14-23 (1998) |
| 1997 | ||
| 4 | EE | Jeffrey L. Burns, Jack A. Feldman: C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD 1997: 110-115 |
| 1993 | ||
| 3 | EE | Jack A. Feldman, Israel A. Wagner, Shmuel Wimer: An efficient algorithm for some multirow layout problems. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1178-1185 (1993) |
| 1989 | ||
| 2 | EE | Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer: Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 737-743 (1989) |
| 1987 | ||
| 1 | EE | Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman: Optimal Chaining of CMOS Transistors in a Functional Cell. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 795-801 (1987) |
| 1 | Reuven Bar-Yehuda | [2] |
| 2 | Jeffrey L. Burns | [4] [5] |
| 3 | Ron Y. Pinter | [1] [2] |
| 4 | Israel A. Wagner | [3] |
| 5 | Shmuel Wimer | [1] [2] [3] |