1998 |
19 | EE | Shangzhi Sun,
David Hung-Chang Du,
Hsi-Chuan Chen:
Efficient timing analysis for CMOS circuits considering data dependent delays.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 546-552 (1998) |
1996 |
18 | | Kwang-Ting Cheng,
Angela Krstic,
Hsi-Chuan Chen:
Generation of High Quality Tests for Robustly Untestable Path Delay Faults.
IEEE Trans. Computers 45(12): 1379-1392 (1996) |
17 | EE | Kwang-Ting Cheng,
Hsi-Chuan Chen:
Classification and identification of nonrobust untestable path delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 845-853 (1996) |
1994 |
16 | EE | Kwang-Ting Cheng,
Hsi-Chuan Chen:
Generation of High Quality Non-Robust Tests for Path Delay Faults.
DAC 1994: 365-369 |
15 | | Shangzhi Sun,
David Hung-Chang Du,
Hsi-Chuan Chen:
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays.
ICCD 1994: 156-159 |
14 | | Shangzhi Sun,
David Hung-Chang Du,
Yaun-Chung Hsu,
Hsi-Chuan Chen:
On Valid Clocking for Combinational Circuits.
ICCD 1994: 381-384 |
13 | EE | Siu-Wing Cheng,
Hsi-Chuan Chen,
David Hung-Chang Du,
Andrew Lim:
The role of long and short paths in circuit performance optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 857-864 (1994) |
12 | EE | Li-Ren Liu,
David Hung-Chang Du,
Hsi-Chuan Chen:
An efficient parallel critical path algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 909-919 (1994) |
11 | EE | Li-Ren Liu,
Hsi-Chuan Chen,
David Hung-Chang Du:
The calculation of signal stable ranges in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1016-1023 (1994) |
1993 |
10 | | Hsi-Chuan Chen,
Siu-Wing Cheng,
Yaun-Chung Hsu,
David Hung-Chang Du:
A Path Sensitization Approach to Area Reduction.
ICCD 1993: 73-76 |
9 | | Kwang-Ting Cheng,
Hsi-Chuan Chen:
Delay Testing for Non-Robust Untestable Circuits.
ITC 1993: 954-961 |
8 | EE | Hsi-Chuan Chen,
David Hung-Chang Du,
Li-Ren Liu:
Critical path selection for performance optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 185-195 (1993) |
7 | EE | Hsi-Chuan Chen,
David Hung-Chang Du:
Path sensitization in critical path problem [logic circuit design].
IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 196-207 (1993) |
1992 |
6 | EE | Hsi-Chuan Chen,
David Hung-Chang Du,
Siu-Wing Cheng:
Circuit Enhancement by Eliminating Long False Paths.
DAC 1992: 249-252 |
5 | EE | Siu-Wing Cheng,
Hsi-Chuan Chen,
David Hung-Chang Du,
Andrew Lim:
The Role of Long and Short Paths in Circuit Performance Optimization.
DAC 1992: 543-548 |
1991 |
4 | EE | Li-Ren Liu,
David Hung-Chang Du,
Hsi-Chuan Chen:
An Efficient Parallel Critical Path Algorithm.
DAC 1991: 535-540 |
3 | EE | Hsi-Chuan Chen,
David Hung-Chang Du,
Li-Ren Liu:
Critical Path Selection for Performance Optimization.
DAC 1991: 547-550 |
2 | | Hsi-Chuan Chen,
David Hung-Chang Du:
Path Sensitization in Critical Path Problem.
ICCAD 1991: 208-211 |
1 | | Li-Ren Liu,
Hsi-Chuan Chen,
David Hung-Chang Du:
The Calculation of Signal Stable Ranges in Combinational Circuits.
ICCAD 1991: 312-315 |