Claudio Costi

List of publications from the DBLP Bibliography Server - FAQ

1998

3 EE Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto: Clock skew reduction in ASIC logic design: a methodology for clock tree management. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 344-356 (1998)

1995

2 EE Claudio Costi, Micaela Serra, Donatella Sciuto: A new DFT methodology for sequential circuits. J. Electronic Testing 7(3): 223-240 (1995)

1994

1 Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto: From Behavioral Description to Systolic Array Based Architectures. EDAC-ETC-EUROASIC 1994: 657

1998
3	EE	Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto: Clock skew reduction in ASIC logic design: a methodology for clock tree management. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 344-356 (1998)
1995
2	EE	Claudio Costi, Micaela Serra, Donatella Sciuto: A new DFT methodology for sequential circuits. J. Electronic Testing 7(3): 223-240 (1995)
1994
1		Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto: From Behavioral Description to Systolic Array Based Architectures. EDAC-ETC-EUROASIC 1994: 657

Coauthor Index