DATE 2004:
Paris,
France
2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France.
IEEE Computer Society 2004, ISBN 0-7695-2085-5 BibTeX
@proceedings{DBLP:conf/date/2004,
title = {2004 Design, Automation and Test in Europe Conference and Exposition
(DATE 2004), 16-20 February 2004, Paris, France},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {2004},
isbn = {0-7695-2085-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Volume 1 - 2 - Designers Forum
Performances Analysis for MPSoC
- Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon:
Analyzing On-Chip Communication in a MPSoC Environment.
752-757
Electronic Edition (link) BibTeX
- Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert:
A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC.
758-763
Electronic Edition (link) BibTeX
- Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal:
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.
764-769
Electronic Edition (link) BibTeX
- Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv:
A Case Study in Networks-on-Chip Design for Embedded Video.
770-777
Electronic Edition (link) BibTeX
Synthesis for Noise and Manufacturability
Support for BIST
Modelling,
Simulation and Optimisation in Power/Ground/Substrate
Panel Session - Chips of the Future:
Soft,
Crunchy or Hard?
Power-Aware Networks and Interfaces
Networks on Chip Design
- Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage:
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
878-883
Electronic Edition (link) BibTeX
- Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.
884-889
Electronic Edition (link) BibTeX
- Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch:
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.
890-895
Electronic Edition (link) BibTeX
- Srinivasan Murali, Giovanni De Micheli:
Bandwidth-Constrained Mapping of Cores onto NoC Architectures.
896-903
Electronic Edition (link) BibTeX
Advances in Technology Mapping and Circuit Sizing
Panel Session - Nanometer Design - What are the Requirements for Manufacturing Test?
Issues in Interconnect Simulation and Model Order Reduction
Emerging Technologies:
From Sensors to Qubits
Embedded Tutorial - Architectures and Design Techniques for Energy-Efficient Embedded DSP and Multimedia Processing
Platform-Based Design and VC Reuse Methods
- Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel:
Measurement of IP Qualification Costs and Benefits.
996-1001
Electronic Edition (link) BibTeX
- Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Architecture-Level Performance Estimation for IP-Based Embedded Systems.
1002-1007
Electronic Edition (link) BibTeX
- Montek Singh, Michael Theobald:
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures.
1008-1013
Electronic Edition (link) BibTeX
- M. Bolado, Hector Posadas, Javier Castillo, P. Huerta, Pablo Sánchez, C. Sánchez, H. Fouren, Francisco Blasco:
Platform Based on Open-Source Cores for Industrial Applications.
1014-1019
Electronic Edition (link) BibTeX
- Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan:
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.
1020-1027
Electronic Edition (link) BibTeX
Real-Time Issues in Embedded Systems
- Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal:
Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application.
1027-1033
Electronic Edition (link) BibTeX
- Yudong Tan, Vincent John Mooney III:
Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches.
1034-1039
Electronic Edition (link) BibTeX
- Alexander Maxiaguine, Simon Künzli, Lothar Thiele:
Workload Characterization Model for Tasks with Variable Execution Demand.
1040-1045
Electronic Edition (link) BibTeX
- Marek Jersak, Rafik Henia, Rolf Ernst:
Context-Aware Performance Analysis for Efficient Embedded System Design.
1046-1051
Electronic Edition (link) BibTeX
- Stacey Shogan, Bruce R. Childers:
Compact Binaries with Code Compression in a Software Dynamic Translator.
1052-1059
Electronic Edition (link) BibTeX
Real-Life Defect Modelling and Detection
- Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng:
Pattern Selection for Testing of Deep Sub-Micron Timing Defects.
160
Electronic Edition (link) BibTeX
- Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer:
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects.
1066-1071
Electronic Edition (link) BibTeX
- Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung:
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.
1072-1077
Electronic Edition (link) BibTeX
- Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
1078-1083
Electronic Edition (link) BibTeX
- Zaid Al-Ars, A. J. van de Goor:
Soft Faults and the Importance of Stresses in Memory Testing.
1084-1091
Electronic Edition (link) BibTeX
Optimisation in Physical Design
Hot Topic - Platforms and Tools for Energy-Efficient Design of Multimedia Systems
Communication Design for MPSoC
- Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya:
Unified Component Integration Flow for Multi-Processor SoC Design and Validation.
1132-1137
Electronic Edition (link) BibTeX
- Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi:
An Interconnect Channel Design Methodology for High Performance Integrated Circuits.
1138-1143
Electronic Edition (link) BibTeX
- Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas:
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach.
1144-1149
Electronic Edition (link) BibTeX
- Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee:
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems.
1150-1157
Electronic Edition (link) BibTeX
Combining Static and Dynamic Software Optimisation
Hot Topic - The Status of the New IEEE Test Standards
Modelling and Estimation in Circuit Layout
Applications of Reconfigurability
- Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno:
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform.
1218-1223
Electronic Edition (link) BibTeX
- Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins:
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.
1224-1229
Electronic Edition (link) BibTeX
- Sami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed, Nizamettin Aydin, Tughrul Arslan, Fred Westall:
Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays.
1230-1235
Electronic Edition (link) BibTeX
- Helena Krupnova:
Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience.
1236-1243
Electronic Edition (link) BibTeX
Interconnect Modelling for MPSoC
Embedded Software Generation and Optimisation
- Manish Verma, Lars Wehmeyer, Peter Marwedel:
Cache-Aware Scratchpad Allocation Algorithm.
1264-1269
Electronic Edition (link) BibTeX
- Markus Lorenz, Peter Marwedel:
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm.
1270-1275
Electronic Edition (link) BibTeX
- Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
1276-1283
Electronic Edition (link) BibTeX
Scan-Based Testing
Novel Approaches to Analogue Simulation
- Bo Wan, C.-J. Richard Shi:
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.
1310-1315
Electronic Edition (link) BibTeX
- Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang:
Direct Nonlinear Order Reduction with Variational Analysis.
1316-1321
Electronic Edition (link) BibTeX
- Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
1322-1326
Electronic Edition (link) BibTeX
- Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.
1327-1333
Electronic Edition (link) BibTeX
Embedded Tutorial - System Verilog for VHDL Users
Hot Topic - Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems
Interactive Presentations
- Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout:
Adaptive Prefetching for Multimedia Applications in Embedded Systems.
1350-1351
Electronic Edition (link) BibTeX
- Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir:
Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases.
1352-1353
Electronic Edition (link) BibTeX
- George F. Viamontes, Igor L. Markov, John P. Hayes:
High-Performance QuIDD-Based Simulation of Quantum Circuits.
1354-1355
Electronic Edition (link) BibTeX
- D. K. Reed, Steven P. Levitan, J. Boles, Jose A. Martinez, Donald M. Chiarulli:
An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation.
1356-1357
Electronic Edition (link) BibTeX
- Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Fault Tolerance of Programmable Switch Blocks.
1358-1359
Electronic Edition (link) BibTeX
- Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel:
A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.
1360-1361
Electronic Edition (link) BibTeX
- Luis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González:
A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation.
1362-1363
Electronic Edition (link) BibTeX
- Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri:
Accurate Estimation of Parasitic Capacitances in Analog Circuits.
1364-1365
Electronic Edition (link) BibTeX
- Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha:
GRAAL - A Development Framework for Embedded Graphics Accelerators.
1366-1367
Electronic Edition (link) BibTeX
- Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou:
From Synchronous to Asynchronous: An Automatic Approach.
1368-1369
Electronic Edition (link) BibTeX
- Oussama Laouamri, Chouki Aktouf:
Enhancing Testability of System on Chips Using Network Management Protocols.
1370-1371
Electronic Edition (link) BibTeX
- Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger:
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.
1372-1373
Electronic Edition (link) BibTeX
- Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu:
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.
1374-1375
Electronic Edition (link) BibTeX
- André C. Nácul, Tony Givargis:
Dynamic Voltage and Cache Reconfiguration for Low Power.
1376-1379
Electronic Edition (link) BibTeX
- Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft:
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models.
1380-1381
Electronic Edition (link) BibTeX
- Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava:
Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software.
1382-1383
Electronic Edition (link) BibTeX
- Abhinav Agrawal, Niraj K. Jha:
Synthesis of Reversible Logic.
1384-1385
Electronic Edition (link) BibTeX
- Matthew M. Ziegler, Mircea R. Stan:
A Unified Design Space for Regular Parallel Prefix Adders.
1386-1387
Electronic Edition (link) BibTeX
- Abusaleh M. Jabir, Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
1388-1389
Electronic Edition (link) BibTeX
- Mario R. Casu, Luca Macchiarulo:
Issues in Implementing Latency Insensitive Protocols.
1390-1391
Electronic Edition (link) BibTeX
- Tim Schattkowsky, Wolfgang Müller:
Model-Based Specification and Execution of Embedded Real-Time Systems.
1392-1393
Electronic Edition (link) BibTeX
- Satnam Singh:
A Demonstration of Co-Design and Co-Verification in a Synchronous Language.
1394-1395
Electronic Edition (link) BibTeX
- Shukang Zhou, Bruce R. Childers, Naveen Kumar:
Profile Guided Management of Code Partitions for Embedded Systems.
1396-1399
Electronic Edition (link) BibTeX
- Rong Jiang, Charlie Chung-Ping Chen:
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects.
1400-1401
Electronic Edition (link) BibTeX
- Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten:
Statistically Aware Buffer Planning.
1402-1403
Electronic Edition (link) BibTeX
- S. Bernardini, Jean Michel Portal, Pascal Masson:
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology.
1404-1405
Electronic Edition (link) BibTeX
- Josep Rius Vázquez, José Pineda de Gyvez:
Power Supply Noise Monitor for Signal Integrity Faults.
1406-1407
Electronic Edition (link) BibTeX
- Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Testing of Quantum Dot Cellular Automata Based Designs.
1408-1409
Electronic Edition (link) BibTeX
- Jacob R. Minz, Mohit Pathak, Sung Kyu Lim:
Net and Pin Distribution for 3D Package Global Routing.
1410-1411
Electronic Edition (link) BibTeX
- Markus Olbrich, Erich Barke:
Placement Using a Localization Probability Model (LPM).
1412
Electronic Edition (link) BibTeX
- Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost:
CMOS Structures Suitable for Secured Hardware.
1414-1415
Electronic Edition (link) BibTeX
- Kambiz Rahimi, Seth Bridges, Chris Diorio:
Timing Correction and Optimization with Adaptive Delay Sequential Element.
1416
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:05:44 2009
by Michael Ley (ley@uni-trier.de)
