| 2008 |
|---|
| 12 | EE | Rashid Muhammad,
Ludovic Apvrille,
Renaud Pacalet:
Application Specific Processors for Multimedia Applications.
CSE 2008: 109-116 |
| 11 | EE | Sylvain Guilley,
Laurent Sauvage,
Jean-Luc Danger,
Nidhal Selmane,
Renaud Pacalet:
Silicon-level Solutions to Counteract Passive and Active Attacks.
FDTC 2008: 3-17 |
| 10 | EE | Rashid Muhammad,
Ludovic Apvrille,
Renaud Pacalet:
Evaluation of ASIPs Design with LISATek.
SAMOS 2008: 177-186 |
| 9 | EE | Sylvain Guilley,
Laurent Sauvage,
Philippe Hoogvorst,
Renaud Pacalet,
Guido Marco Bertoni,
Sumanta Chaudhuri:
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.
IEEE Trans. Computers 57(11): 1482-1497 (2008) |
| 2007 |
|---|
| 8 | EE | Sylvain Guilley,
Florent Flament,
Philippe Hoogvorst,
Renaud Pacalet,
Yves Mathieu:
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.
IEEE Design & Test of Computers 24(6): 546-555 (2007) |
| 7 | EE | Sylvain Guilley,
Philippe Hoogvorst,
Renaud Pacalet:
A fast pipelined multi-mode DES architecture operating in IP representation.
Integration 40(4): 479-489 (2007) |
| 2006 |
|---|
| 6 | EE | Muhammad Waseem,
Ludovic Apvrille,
Rabéa Ameur-Boulifa,
Sophie Coudert,
Renaud Pacalet:
Abstract Application Modeling for System Design Space Exploration.
DSD 2006: 331-337 |
| 2005 |
|---|
| 5 | EE | Sylvain Guilley,
Philippe Hoogvorst,
Yves Mathieu,
Renaud Pacalet:
The "Backend Duplication" Method.
CHES 2005: 383-397 |
| 2004 |
|---|
| 4 | | Sylvain Guilley,
Philippe Hoogvorst,
Renaud Pacalet:
Differential Power Analysis Model and Some Results.
CARDIS 2004: 127-142 |
| 3 | EE | Sylvain Guilley,
Philippe Hoogvorst,
Yves Mathieu,
Renaud Pacalet,
Jean Provost:
CMOS Structures Suitable for Secured Hardware.
DATE 2004: 1414-1415 |
| 1999 |
|---|
| 2 | EE | Stéphane Mancini,
Renaud Pacalet:
LUX: An Heterogeneous Function Composition Parallel Computer for Graphics.
Euro-Par 1999: 940-949 |
| 1997 |
|---|
| 1 | EE | Carolina Miro,
Nicolas Darbel,
Renaud Pacalet,
Valerie Paquet:
A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor.
ASAP 1997: 86-95 |
