dblp.uni-trier.dewww.uni-trier.de

Philippe Hoogvorst

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
16EESumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
15EESumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125
14EESumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley: Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257
13EESylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst: Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166
12EESylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32
11EESumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger: Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18
10EEPhilippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR abs/0809.3942: (2008)
9EESylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri: Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57(11): 1482-1497 (2008)
2007
8 Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
7EESylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu: Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers 24(6): 546-555 (2007)
6EESylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: A fast pipelined multi-mode DES architecture operating in IP representation. Integration 40(4): 479-489 (2007)
2005
5EESylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet: The "Backend Duplication" Method. CHES 2005: 383-397
4 Sylvain Guilley, Philippe Hoogvorst: The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations. SEC 2005: 589-600
2004
3 Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: Differential Power Analysis Model and Some Results. CARDIS 2004: 127-142
2EESylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost: CMOS Structures Suitable for Secured Hardware. DATE 2004: 1414-1415
1991
1 Philippe Hoogvorst, Ronan Keryell, Philippe Matherat, Nicolas Paris: POMP or How to Design a Massively Parallel Machine with Small Developments. PARLE (1) 1991: 83-100

Coauthor Index

1Guido Bertoni (Guido Marco Bertoni) [9]
2Taha Beyrouthy [8] [10] [16]
3Sumanta Chaudhuri [8] [9] [10] [11] [12] [14] [15] [16]
4Jean-Luc Danger [10] [11] [12] [13] [14] [15] [16]
5Laurent Fesquet [8] [10] [16]
6Florent Flament [7] [15]
7Tarik Graba [12]
8Sylvain Guilley [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
9Ronan Keryell [1]
10Philippe Matherat [1]
11Yves Mathieu [2] [5] [7]
12Maxime Nassar [12]
13Renaud Pacalet [2] [3] [5] [6] [7] [9]
14Nicolas Paris [1]
15Jean Provost [2]
16Alin Razafindraibe [8] [16]
17Marc Renaudin [16]
18Laurent Sauvage [9] [12] [13]
19Vinh-Nga Vong [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)