R. G. Bennetts
List of publications from the
2007 |
16 | EE | Ben Bennetts:
Electronics Design-for-Test: Past, Present and Future.
European Test Symposium 2007: 4 |
2006 |
15 | EE | Bill Eklow,
Ben Bennetts:
New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).
European Test Symposium 2006: 253-254 |
2004 |
14 | EE | Stephen K. Sunter,
Adam Osseiran,
Adam Cron,
Neil Jacobson,
Dave Bonnett,
Bill Eklow,
Carl Barnhart,
Ben Bennetts:
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6.
DATE 2004: 1184-1191 |
2003 |
13 | EE | Monica Lobetti Bodoni,
Ben Bennetts:
Guest Editors' Introduction: Board Test.
IEEE Design & Test of Computers 20(2): 5-7 (2003) |
12 | EE | Erik Jan Marinissen,
Bart Vermeulen,
Henk D. L. Hollmann,
Ben Bennetts:
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.
IEEE Design & Test of Computers 20(2): 8-18 (2003) |
1999 |
11 | | Tony Ambler,
Ben Bennetts:
Guest Editors' Introduction: Test and the Product Life Cycle.
IEEE Design & Test of Computers 16(3): 20-22 (1999) |
10 | EE | Mike Wondolowski,
Ben Bennetts,
Adam W. Ley:
Boundary Scan: The Internet of Test.
IEEE Design & Test of Computers 16(3): 34-43 (1999) |
1996 |
9 | | Bernd Könemann,
Ben Bennetts,
Najmi T. Jarwala,
Benoit Nadeau-Dostie:
Built-In Self-Test: Assuring System Integrity.
IEEE Computer 29(11): 39-45 (1996) |
1995 |
8 | | Ben Bennetts:
Guest Editor's Introduction.
IEEE Design & Test of Computers 12(2): 6-7 (1995) |
1992 |
7 | | Ben Bennetts:
Progress in DFT: A Personal View.
ITC 1992: 19-20 |
6 | | Frank Bouwman,
Steven Oostdijk,
Rudi Stans,
Ben Bennetts,
Frans P. M. Beenker:
Macro Testability: The Results of Production Device Applications.
ITC 1992: 232-241 |
1991 |
5 | | R. G. Bennetts:
Scan Technology at Work.
Fault-Tolerant Computing Systems 1991: 124-135 |
4 | EE | R. G. Bennetts,
A. Osseyran:
IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status.
J. Electronic Testing 2(1): 11-25 (1991) |
1990 |
3 | | Ben Bennetts:
Test Technology in Europe.
IEEE Design & Test of Computers 7(1): 6-8 (1990) |
1972 |
2 | EE | R. G. Bennetts:
A realistic approach to detection test generation for combinatorial logic circuits.
Comput. J. 15(3): 238-246 (1972) |
1971 |
1 | | Ben Bennetts,
D. W. Lewin:
Fault Diagnosis of Digital Systems - A Review.
Comput. J. 14(2): 199-206 (1971) |