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Hidenari Nakashima

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2007
7EEKoutaro Hachiya, Takayuki Ohshima, Hidenari Nakashima, Masaaki Soda, Satoshi Goto: Fast Methods to Estimate Clock Jitter due to Power Supply Noise. IEICE Transactions 90-A(4): 741-747 (2007)
6EEHiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto: Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Transactions 90-A(4): 808-814 (2007)
2005
5EETakanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI 2005: 276-277
4EEHidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Transactions 88-A(12): 3358-3366 (2005)
3EEHidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu: Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Transactions 88-A(12): 3437-3444 (2005)
2EETakanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model for System LSI. IEICE Transactions 88-A(12): 3445-3452 (2005)
2004
1EEHidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu: ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE 2004: 1210-1217

Coauthor Index

1Satoshi Goto [7]
2Koutaro Hachiya [7]
3Masanori Hashimoto [6]
4Junpei Inoue [1] [2] [3] [4] [5]
5Jiro Iwai [6]
6Hiroyuki Kobayashi [6]
7Takanori Kyogoku [2] [5]
8Kazuya Masu [1] [2] [3] [4] [5]
9Takayuki Ohshima [7]
10Kenichi Okada [1] [2] [3] [4] [5]
11Takaaki Okumura [6]
12Nobuto Ono [6]
13Takashi Sato [6]
14Masaaki Soda [7]
15Naohiro Takagi [3]
16Takumi Uezono [2] [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)