| 2007 |
|---|
| 7 | EE | Koutaro Hachiya,
Takayuki Ohshima,
Hidenari Nakashima,
Masaaki Soda,
Satoshi Goto:
Fast Methods to Estimate Clock Jitter due to Power Supply Noise.
IEICE Transactions 90-A(4): 741-747 (2007) |
| 6 | EE | Hiroyuki Kobayashi,
Nobuto Ono,
Takashi Sato,
Jiro Iwai,
Hidenari Nakashima,
Takaaki Okumura,
Masanori Hashimoto:
Proposal of Metrics for SSTA Accuracy Evaluation.
IEICE Transactions 90-A(4): 808-814 (2007) |
| 2005 |
|---|
| 5 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model Considering Core Utilization for System on Chip.
ISVLSI 2005: 276-277 |
| 4 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Transactions 88-A(12): 3358-3366 (2005) |
| 3 | EE | Hidenari Nakashima,
Naohiro Takagi,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Transactions 88-A(12): 3437-3444 (2005) |
| 2 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model for System LSI.
IEICE Transactions 88-A(12): 3445-3452 (2005) |
| 2004 |
|---|
| 1 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
ULSI Interconnect Length Distribution Model Considering Core Utilization.
DATE 2004: 1210-1217 |
