| 2005 |
|---|
| 7 | EE | Junpei Inoue,
Hiroyuki Ito,
Shinichiro Gomi,
Takanori Kyogoku,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Evaluation of on-chip transmission line interconnect using wire length distribution.
ASP-DAC 2005: 133-138 |
| 6 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model Considering Core Utilization for System on Chip.
ISVLSI 2005: 276-277 |
| 5 | EE | Takumi Uezono,
Junpei Inoue,
Takanori Kyogoku,
Kenichi Okada,
Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects.
SLIP 2005: 7-12 |
| 4 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Transactions 88-A(12): 3358-3366 (2005) |
| 3 | EE | Hidenari Nakashima,
Naohiro Takagi,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Transactions 88-A(12): 3437-3444 (2005) |
| 2 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model for System LSI.
IEICE Transactions 88-A(12): 3445-3452 (2005) |
| 2004 |
|---|
| 1 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
ULSI Interconnect Length Distribution Model Considering Core Utilization.
DATE 2004: 1210-1217 |
