dblp.uni-trier.dewww.uni-trier.de

Juan L. Aragón

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
14EEAntonio Flores, Manuel E. Acacio, Juan L. Aragón: Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303
13EEJuan L. Aragón, Alexander V. Veidenbaum: Optimizing CAM-based instruction cache designs for low-power embedded systems. Journal of Systems Architecture - Embedded Systems Design 54(12): 1155-1163 (2008)
12EEAntonio Flores, Juan L. Aragón, Manuel E. Acacio: An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. The Journal of Supercomputing 45(3): 341-364 (2008)
2007
11EEAntonio Flores, Juan L. Aragón, Manuel E. Acacio: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757
10EEJuan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras: Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. Conf. Computing Frontiers 2007: 113-122
9EEAntonio Flores, Juan L. Aragón, Manuel E. Acacio: Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146
8EEJuan M. Cebrian, Juan L. Aragón, José M. García: Leakage Energy Reduction in Value Predictors through Static Decay. IPDPS 2007: 1-7
2006
7EEJuan L. Aragón, José M. González, Antonio González: Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. IEEE Trans. Computers 55(3): 281-291 (2006)
2005
6EEJuan L. Aragón, Alexander V. Veidenbaum: Energy-Effective Instruction Fetch Unit for Wide Issue Processors. Asia-Pacific Computer Systems Architecture Conference 2005: 15-27
2004
5EEJuan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. DATE 2004: 1374-1375
2003
4EEJuan L. Aragón, José González, Antonio González: Power-Aware Control Speculation through Selective Throttling. HPCA 2003: 103-112
2002
3EEJuan L. Aragón, José González, Antonio González, James E. Smith: Dual path instruction processing. ICS 2002: 220-229
2001
2EEJuan L. Aragón, José González, José M. García, Antonio González: Confidence Estimation for Branch Prediction Reversal. HiPC 2001: 214-223
1 Juan L. Aragón, José González, José M. García, Antonio González: Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. ICCD 2001: 228-233

Coauthor Index

1Manuel E. Acacio [9] [11] [12] [14]
2Ana-Maria Badulescu [5]
3Juan M. Cebrian [8] [10]
4Antonio Flores [9] [11] [12] [14]
5José M. García [1] [2] [8] [10]
6Antonio González [1] [2] [3] [4] [7]
7José González [1] [2] [3] [4]
8José M. González [7]
9Stefanos Kaxiras [10]
10Dan Nicolaescu [5]
11James E. Smith [3]
12Alexander V. Veidenbaum [5] [6] [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)