| 2005 |
|---|
| 8 | EE | Anuradha Agarwal,
Glenn Wolfe,
Ranga Vemuri:
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.
ACM Great Lakes Symposium on VLSI 2005: 482-487 |
| 7 | | Anuradha Agarwal,
Ranga Vemuri:
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.
ICCAD 2005: 430-436 |
| 6 | EE | Anuradha Agarwal,
Ranga Vemuri:
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.
ICCD 2005: 444-452 |
| 5 | EE | Huiying Yang,
Anuradha Agarwal,
Ranga Vemuri:
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams.
ISVLSI 2005: 71-76 |
| 2004 |
|---|
| 4 | EE | Raoul F. Badaoui,
Hemanth Sampath,
Anuradha Agarwal,
Ranga Vemuri:
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.
ACM Great Lakes Symposium on VLSI 2004: 271-276 |
| 3 | EE | Anuradha Agarwal,
Hemanth Sampath,
Veena Yelamanchili,
Ranga Vemuri:
Fast and accurate parasitic capacitance models for layout-aware.
DAC 2004: 145-150 |
| 2 | EE | Anuradha Agarwal,
Hemanth Sampath,
Veena Yelamanchili,
Ranga Vemuri:
Accurate Estimation of Parasitic Capacitances in Analog Circuits.
DATE 2004: 1364-1365 |
| 1 | EE | Mukesh Ranjan,
Wim Verhaegen,
Anuradha Agarwal,
Hemanth Sampath,
Ranga Vemuri,
Georges G. E. Gielen:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
DATE 2004: 604-609 |
