Helena Krupnova

2004
15	EE	Helena Krupnova: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience. DATE 2004: 1236-1243
14	EE	A. Bigot, F. Charpentier, Helena Krupnova, I. Sans: Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. FPL 2004: 64-73
2002
13	EE	Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi: How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. FPL 2002: 26-35
2000
12	EE	Helena Krupnova, Gabriele Saucier: FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. FPL 2000: 68-77
11	EE	Helena Krupnova, Gabriele Saucier: FPGA Technology Snapshot: Current Devices and Design Tools. IEEE International Workshop on Rapid System Prototyping 2000: 200-
1999
10	EE	Helena Krupnova, Gabriele Saucier: Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. DATE 1999: 587-
9	EE	Helena Krupnova, Gabriele Saucier: Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. FPGA 1999: 251
8		Helena Krupnova, Gabriele Saucier: Hierarchical Interactive Approach to Partition Large Designs into FPGAs. FPL 1999: 101-110
7	EE	Helena Krupnova, Christian Rabedaoro, Gabriele Saucier: FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping 1999: 128-133
1998
6	EE	Helena Krupnova, B. Behnam, Gabriele Saucier: Block and IP Wrapping for Efficient Design on FPGAs (Abstract). FPGA 1998: 256
5	EE	S. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier: Timing Driven Floorplanning on Programmable Hierarchical Targets. FPGA 1998: 85-92
4	EE	Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier: A Knowledge-Based System for Prototyping on FPFAs. FPL 1998: 89-98
3	EE	Helena Krupnova, D. D. A. Vu, Gabriele Saucier, M. Boubal: Real Time Prototyping Method and a Case Study. International Workshop on Rapid System Prototyping 1998: 13-18
1997
2	EE	Helena Krupnova, Ali Abbara, Gabriele Saucier: A Hierarchy-Driven FPGA Partitioning Method. DAC 1997: 522-525
1	EE	Helena Krupnova, Christian Rabedaoro, Gabriele Saucier: Synthesis and Floorplanning for Large Hierarchical FPGAs. FPGA 1997: 105-111

Coauthor Index

1	Ali Abbara	[2]
2	A. Amoura	[5]
3	Christophe Barnichon	[13]
4	B. Behnam	[6]
5	A. Bigot	[14]
6	M. Boubal	[3]
7	F. Charpentier	[14]
8	Vu DucAnh Dinh	[4]
9	Veronique Meurou	[13]
10	Farid Morsi	[13]
11	Christian Rabedaoro	[1] [7]
12	I. Sans	[14]
13	Gabriele Saucier	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
14	S. A. Senouci	[5]
15	Carlos Serra	[13]
16	D. D. A. Vu	[3]

Colors in the list of coauthors