Andreas Wieferink

2008
12	EE	Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr: SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. IJES 3(3): 109-118 (2008)
11	EE	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. IJES 3(3): 150-159 (2008)
2007
10	EE	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embedded Comput. Syst. 6(2): (2007)
2005
9	EE	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254
2004
8	EE	Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263
7	EE	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148
6	EE	Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452
5	EE	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46
2003
4	EE	Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann: Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. ASAP 2003: 161-171
3	EE	Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12
2	EE	Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973
2001
1	EE	Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001)

Coauthor Index

1	Gerd Ascheid	[3] [5] [6] [7] [8] [9] [10]
2	Gunnar Braun	[1] [2] [8]
3	Jianjiang Ceng	[5] [10]
4	Malte Doerper	[3] [6] [7] [11]
5	Serge Goossens	[3]
6	Andreas Hoffmann	[1] [4]
7	Manuel Hohenauer	[5] [10]
8	David Kammler	[5] [10]
9	Kingshuk Karuri	[5] [10]
10	Torsten Kempf	[7] [11]
11	Tim Kogel	[1] [3] [4] [6] [7] [8] [9] [11] [12]
12	Rainer Leupers	[2] [3] [5] [6] [7] [8] [9] [10] [11] [12]
13	Heinrich Meyr	[1] [2] [3] [5] [6] [7] [8] [9] [10] [11] [12]
14	Tom Michiels	[9]
15	Achim Nohl	[1] [2] [4] [8] [9]
16	Hanno Scharwächter	[5] [10]
17	Oliver Schliebusch	[1] [2]
18	Oliver Wahlen	[1]
19	Olaf Zerres	[12]