| 2005 |
|---|
| 4 | EE | Takashi Mine,
Hidemasa Kubota,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits.
ISCAS (5) 2005: 4903-4906 |
| 2004 |
|---|
| 3 | EE | Takashi Mine,
Hidemasa Kubota,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits.
DATE 2004: 1327-1333 |
| 2001 |
|---|
| 2 | EE | Atsushi Kamo,
Takayuki Watanabe,
A. Asai:
Simulation for the optimal placement of decoupling capacitors on printed circuit board.
ISCAS (3) 2001: 727-730 |
| 1 | EE | Masaya Suzuki,
H. Miyashita,
Atsushi Kamo,
Takayuki Watanabe,
Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method.
ISCAS (5) 2001: 327-330 |
