DATE 2004:
Paris,
France
2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France.
IEEE Computer Society 2004, ISBN 0-7695-2085-5 BibTeX
@proceedings{DBLP:conf/date/2004,
title = {2004 Design, Automation and Test in Europe Conference and Exposition
(DATE 2004), 16-20 February 2004, Paris, France},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {2004},
isbn = {0-7695-2085-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Volume 1 - 2 - Designers Forum
Hot Topic - From Working Design Flow to Working Chips:
Dependencies and Impacts of Methodology Decisions
Analogue and RF Design
- Adão Antônio de Souza Jr., Luigi Carro:
Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs.
10-15
Electronic Edition (link) BibTeX
- Faress Tissafi-Drissi, Ian O'Connor, Frédéric Gaffiot:
RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends.
16-21
Electronic Edition (link) BibTeX
- Yiming Chen, Xiaojuen Yuan, David Scagnelli, James Mecke, Jeff Gross, David L. Harame:
Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology.
22-27
Electronic Edition (link) BibTeX
- Peter H. Saul:
Low Power Analogue 90 Degree Phase Shifter.
28-33
Electronic Edition (link) BibTeX
- Pavel Horsky:
A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications.
34-38
Electronic Edition (link) BibTeX
- Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis:
An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain.
39-45
Electronic Edition (link) BibTeX
Platform and IP Design
- Andreas Wortmann, Sven Simon, Matthias Müller:
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.
46-51
Electronic Edition (link) BibTeX
- Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi:
Design of Very Deep Pipelined Multipliers for FPGAs.
52-57
Electronic Edition (link) BibTeX
- Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard:
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding.
58-63
Electronic Edition (link) BibTeX
- A. P. Niranjan, Paul C. Wiscombe:
Islands of Synchronicity, a Design Methodology for SoC Design.
64-69
Electronic Edition (link) BibTeX
- Luigi Dadda, Marco Macchetti, Jeff Owen:
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512).
70-75
Electronic Edition (link) BibTeX
- Chang Hong Lin, Yuan Xie, Wayne Wolf:
LZW-Based Code Compression for VLIW Embedded Systems.
76-81
Electronic Edition (link) BibTeX
- Rocco Le Moigne, Olivier Pasquier, Jean Paul Calvez:
A Generic RTOS Model for Real-time Systems Simulation with SystemC.
82-87
Electronic Edition (link) BibTeX
- Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken:
A Scalable Architecture for LDPC Decodin.
88-95
Electronic Edition (link) BibTeX
Design Verification and Test
- Stephen Schmitt, Wolfgang Rosenstiel:
Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments.
96-101
Electronic Edition (link) BibTeX
- Alexander Krupp, Wolfgang Müller, Ian Oliver:
Formal Refinement and Model Checking of an Echo Cancellation Unit.
102-107
Electronic Edition (link) BibTeX
- Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk:
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip.
108-113
Electronic Edition (link) BibTeX
- Tobias Thiel:
Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice.
114-119
Electronic Edition (link) BibTeX
- Vlado Vorisek, Thomas Koch, Hermann Fischer:
At-Speed Testing of SOC ICs.
120-125
Electronic Edition (link) BibTeX
- Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
Utilizing Formal Assertions for System Design of Network Processors.
126-133
Electronic Edition (link) BibTeX
Design Methodology
- Juan C. Diaz, Marta Saburit:
Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit.
134-139
Electronic Edition (link) BibTeX
- Richard Auletta:
Expert System Perimeter Block Placement Floorplanning.
140-143
Electronic Edition (link) BibTeX
- Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, H. Smith:
A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.
144-149
Electronic Edition (link) BibTeX
- Jesús Ruiz-Amaya, Josep Lluís de la Rosa, F. Medeiro, Francisco V. Fernández, Rocio del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators.
150-155
Electronic Edition (link) BibTeX
- Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
156-160
Electronic Edition (link) BibTeX
- Ankush Varma, Shuvra S. Bhattacharyya:
Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems.
161-167
Electronic Edition (link) BibTeX
Network Design
- Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla:
Heterogeneous Co-Simulation of Networked Embedded Systems.
168-173
Electronic Edition (link) BibTeX
- Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia, Francesco Papariello:
OCCN: A Network-On-Chip Modeling and Simulation Framework.
174-179
Electronic Edition (link) BibTeX
- Francesco Bruschi, Massimo Bombana:
A Design Methodology for the Exploitation of High Level Communication Synthesis.
180-185
Electronic Edition (link) BibTeX
- Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos:
Software Processing Performance in Network Processors.
186-191
Electronic Edition (link) BibTeX
- Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn:
Channel Decoder Architecture for 3G Mobile Wireless Terminals.
192-197
Electronic Edition (link) BibTeX
- Cesar Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin:
RASoC: A Router Soft-Core for Networks-on-Chip.
198-205
Electronic Edition (link) BibTeX
Reconfigurable Architecture
- Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese:
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware.
206-211
Electronic Edition (link) BibTeX
- Hala A. Farouk, Magdy Saeb:
Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA.
212-217
Electronic Edition (link) BibTeX
- Daniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael Canetti:
NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices.
218-223
Electronic Edition (link) BibTeX
- Roger Endrigo Carvalho Porto, Luciano Volcan Agostini:
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.
224-229
Electronic Edition (link) BibTeX
- Marc Quax, Jos Huisken, Jef L. van Meerbergen:
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver.
230-235
Electronic Edition (link) BibTeX
- W. W. S. Chu, R. G. Dimond, S. Perrott, S. P. Seng, W. Luk:
Customisable EPIC Processor: Architecture and Tools.
236-241
Electronic Edition (link) BibTeX
- Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi:
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications.
242-247
Electronic Edition (link) BibTeX
- Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel:
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks.
248-255
Electronic Edition (link) BibTeX
Constrained and Domain Specific Architectures
- Sara Blanc, Joaquin Gracia, Pedro J. Gil:
Experiences during the Experimental Validation of the Time-Triggered Architecture.
256-261
Electronic Edition (link) BibTeX
- Thorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel:
Evaluation of a Refinement-Driven SystemC'-Based Design Flow.
262-267
Electronic Edition (link) BibTeX
- Nico Bannow, Karsten Haug:
Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications.
268-273
Electronic Edition (link) BibTeX
- W. J. Bainbridge, Luis A. Plana, Stephen B. Furber:
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.
274-279
Electronic Edition (link) BibTeX
- Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai:
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.
280-285
Electronic Edition (link) BibTeX
- Jay Abraham, Guruprasad Rao:
Qualification and Integration of Complex I/O in SoC Design Flows.
286-293
Electronic Edition (link) BibTeX
Low Power Design
- Lieven Hollevoet, Andy Dewilde, Kristof Denolf, Francky Catthoor, Filip Louagie:
A Power Optimized Display Memory Organization for Handheld User Terminal.
294-299
Electronic Edition (link) BibTeX
- Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.
300-305
Electronic Edition (link) BibTeX
- Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
Analysis and Modeling of Energy Reducing Source Code Transformations.
306-311
Electronic Edition (link) BibTeX
- Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis:
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
312-317
Electronic Edition (link) BibTeX
- Andrea Bona, Vittorio Zaccaria, Roberto Zafalon:
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip.
318-323
Electronic Edition (link) BibTeX
- Krisztián Flautner, David Flynn, David Roberts, Dipesh I. Patel:
IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling.
324-329
Electronic Edition (link) BibTeX
Interactive Presentations
- Kathy Werner:
Can IP Quality be Objectively Measured?
330-331
Electronic Edition (link) BibTeX
- Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden:
Improving Design and Verification Productivity with VHDL-200x.
332-335
Electronic Edition (link) BibTeX
- Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa:
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.
336-337
Electronic Edition (link) BibTeX
- B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot:
VHDL-AMS Library Development for Pacemaker Applications.
338-341
Electronic Edition (link) BibTeX
- Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Modeling and Analysis of Heterogeneous Industrial Networks Architectures.
342-344 BibTeX
Copyright © Sat May 16 23:05:44 2009
by Michael Ley (ley@uni-trier.de)
