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Masaharu Imai

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2008
37EEYuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP 2008: 150-155
36EEYuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Transactions 91-A(2): 604-612 (2008)
2007
35EETakeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC 2007: 286-291
34EEHirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS 2007: 227-232
33EEYuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
32EEM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC CoRR abs/0710.4746: (2007)
31EEHiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto: Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Transactions 90-A(12): 2800-2809 (2007)
2006
30EEHiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa: Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS 2006: 154-159
29EEIttetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295
2005
28 Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic: Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
27EEM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Enabling RTOS simulation modeling in a system level design language. ASP-DAC 2005: 936-939
26EEMasaharu Imai, Akira Kitajima: Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME 2005: 2
25EEM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE 2005: 554-559
24EEYuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTImedia 2005: 81-86
2004
23 Masaharu Imai: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 IEEE 2004
22EEYuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC 2004: 842-845
21EEKyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007
20EEH. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops 2004: 824-830
19 Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai: S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) 2004: 505-508
2003
18EEHiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai: A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES 2003: 66-80
2002
17EEAkira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai: Design of Application Specific CISC Using PEAS-III. IEEE International Workshop on Rapid System Prototyping 2002: 12-17
2001
16EEAkira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai: Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ASP-DAC 2001: 649-654
15EEHideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai: VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. EUROMICRO 2001: 400-409
2000
14EEMasaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura: One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654
13EEMakiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi: PEAS-III: An ASIP Design Environment. ICCD 2000: 430-436
1999
12EEEiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura: Application of FHM-Based Design Method to Scalable 2-D DCT Processor. EUROMICRO 1999: 1406-1409
1998
11 Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi: A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC 1998: 367-372
1996
10EENguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi: A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC 1996: 527-532
9 Masaharu Imai, Eugenio Villar: ASPDAC 1995: HDL synthesizability and interoperability. IEEE Design & Test of Computers 13(1): 3-4 (1996)
1995
8EENguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi: A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC 1995
7EEMasaharu Imai, Eugenio Villar: Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC 1995
6EEEugenio Villar, Masaharu Imai: Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC 1995
5EEBinh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi: A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC 1995: 176-181
1993
4EEAlauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi: An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD 1993: 526-532
1991
3 Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi: An Integrated Design Environment for Application Specific Integrated Processor. ICCD 1991: 414-417
1986
2 Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki: Implementation of Parallel Prolog on Tree Machines. FJCC 1986: 287-296
1984
1 Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura: The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. ICDCS 1984: 174-182

Coauthor Index

1H. M. AbdElSalam [20]
2Masaaki Abe [35]
3Alauddin Alomary [4]
4Alauddin Y. Alomary [3]
5Hamid R. Arabnia [28]
6Karen Bartleson [14]
7Jürgen Becker [28]
8Nguyen-Ngoc Bình [8] [10] [11]
9Francky Catthoor [24] [33] [36] [37]
10Peter Flake [14]
11Teruo Fukumura [1]
12Daniel Gajski (Daniel D. Gajski) [14]
13Tetsuya Hakata [3]
14M. Abdelsalam Hassan [25] [27] [32]
15Shigeaki Higaki [13]
16Nobuyuki Hikichi [3] [4] [5] [8] [10]
17Yoshimichi Honma [4]
18Toshihide Ibaraki [2]
19Yohei Ishimaru [19]
20Makiko Itoh [13] [16]
21Hirofumi Iwato [34]
22Murali Jayapala [24] [33] [36] [37]
23Tsutomu Kimura [12]
24Akira Kitajima [13] [16] [17] [26]
25Shinsuke Kobayashi [18] [19] [20] [22]
26Yuki Kobayashi [22] [24] [33] [36] [37]
27Nobu Matsumoto [30] [31]
28Hajime Miura [2]
29Masaki Nakagawa [30]
30Takeharu Nakata [4]
31Binh Ngoc Nguyen [5]
32Koji Okuda [22]
33Yutaka Ota [30] [31]
34Praveen Raghavan [24] [33] [36] [37]
35Wolfgang Rosenstiel [14]
36Keishi Sakanushi [18] [19] [20] [21] [22] [25] [27] [29] [30] [31] [32] [34] [35]
37Zoran A. Salcic [28]
38Toshiyuki Sasaki [17]
39Jun Sato [3] [13] [16]
40Steven Schulz [14]
41Eiichirou Shigehara [12]
42Akichika Shiomi [8] [10] [13] [16]
43Takeshi Shiro [35]
44Gary Smith [14]
45Hiroki Tagawa [31]
46Yoshinori Takeuchi [11] [12] [13] [15] [16] [17] [18] [19] [20] [21] [22] [25] [27] [29] [30] [31] [32] [34] [35]
47Hiroaki Tanaka [18] [30] [31]
48Ittetsu Taniguchi [29]
49Yuuji Tateizumi [1]
50Kyoko Ueda [21] [29]
51Eugenio Villar [6] [7] [9]
52Masafumi Yamashita [2]
53Hideki Yamauchi [15]
54Laurence Tianruo Yang [28]
55Hiroto Yasuura [14]
56Yuuji Yoshida [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)