Sylvain Guilley

2008
18	EE	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
17	EE	Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125
16	EE	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet: Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17
15	EE	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley: Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257
14	EE	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst: Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166
13	EE	Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32
12	EE	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger: Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18
11	EE	Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR abs/0809.3942: (2008)
10	EE	Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri: Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57(11): 1482-1497 (2008)
2007
9	EE	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley: Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL 2007: 665-669
8	EE	Qing Xu, M. B. C. Silva, Jean-Luc Danger, Sylvain Guilley, Patrick Bellot, Philippe Gallion, Francisco Mendieta: Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference. RIVF 2007: 158-165
7		Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22
6	EE	Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu: Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers 24(6): 546-555 (2007)
5	EE	Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: A fast pipelined multi-mode DES architecture operating in IP representation. Integration 40(4): 479-489 (2007)
2005
4	EE	Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet: The "Backend Duplication" Method. CHES 2005: 383-397
3		Sylvain Guilley, Philippe Hoogvorst: The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations. SEC 2005: 589-600
2004
2		Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: Differential Power Analysis Model and Some Results. CARDIS 2004: 127-142
1	EE	Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost: CMOS Structures Suitable for Secured Hardware. DATE 2004: 1414-1415

Coauthor Index

1	Patrick Bellot	[8]
2	Guido Bertoni (Guido Marco Bertoni)	[10]
3	Taha Beyrouthy	[7] [11] [18]
4	Sumanta Chaudhuri	[7] [9] [10] [11] [12] [13] [15] [17] [18]
5	Jean-Luc Danger	[8] [9] [11] [12] [13] [14] [15] [16] [17] [18]
6	Laurent Fesquet	[7] [11] [18]
7	Florent Flament	[6] [17]
8	Philippe Gallion	[8]
9	Tarik Graba	[13]
10	Philippe Hoogvorst	[1] [2] [3] [4] [5] [6] [7] [10] [11] [12] [13] [14] [15] [17] [18]
11	Yves Mathieu	[1] [4] [6]
12	Francisco Mendieta	[8]
13	Maxime Nassar	[13]
14	Renaud Pacalet	[1] [2] [4] [5] [6] [10] [16]
15	Jean Provost	[1]
16	Alin Razafindraibe	[7] [18]
17	Marc Renaudin	[18]
18	Laurent Sauvage	[10] [13] [14] [16]
19	Nidhal Selmane	[16]
20	M. B. C. Silva	[8]
21	Vinh-Nga Vong	[13]
22	Qing Xu	[8]